適用以矽智產為基礎之系統晶片設計的高階功率模型研究

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：36

、訪客IP：3.142.130.242

姓名

薛文燦(Wen-Tsan Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用以矽智產為基礎之系統晶片設計的高階功率模型研究
(On High-Level Power Modeling Approaches for IP-Based SOC Designs)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究	★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬	★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器	★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究	★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究	★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計	★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在預估複雜數位電路的功率消耗時，常用功率模型的方式來預估，這個方法因為在使用上不需要電路內部詳細的資訊，所以在非常高的設計層次中，便能預估到電路的功率消耗。目前來說，以功率模型為基礎的功率估測方式，似乎是最適合用在系統晶片的設計環境當中，可以根據不同的輸入狀況，快速地提供此功能區塊對應的功率消耗大小。但是一個系統之中通常包含了各種性質不同的功能區塊，如何針對各種區塊的性質差異，建立適合的高階功率模型，也是一個需要深入探討的課題。在這篇論文中，我們針對系統晶片中的主要的電路類型來提出其相對應的高階功率模型的建構方法。在這裡，我們將主要的電路類型區分成四種：組合邏輯電路區塊，序向邏輯電路區塊，嵌入式記憶體電路區塊，處理器電路區塊。
在組合邏輯電路及序向邏輯電路中，我們著力研究在利用類神經網路來建立一種嶄新的功率消耗模型，利用類神經網路來學習輸入資訊及相對應功率消耗的值，進而應用在高階功率估測上。不同於查表法，透過特徵值萃取處理程序後，我們的模組並不會與電路大小有那麼直接的關係，且因為類神經網路的特性，使得這個簡單的模型還可以擁有很好的準確度。從我們的實驗數據裡可看出，在廣泛的輸入變化範圍內，此功率模型依然保有相當的準確度。
在系統晶片中，嵌入式記憶體常被用廣泛地被使用。為了能更正確地估測出整個設計的功率消耗，一個準確的記憶體功率模型是必需的。但是目前電子自動設計工具所使用的傳統記憶體功率模型都過於簡單，導致功率預估的結果不夠精準。在這篇論文裡，我們便針對這方面提出了兩個方法來試著解決此問題。一個是改進的記憶體功率模型，其主要差別在於將非控制輸入信號的變化也納入考量，以便使功率模型更接近實際電路的功率消耗行為模式。另一方面，為了此方法與現今的電子自動設計工具能一起使用，我們也發展了一套冗餘模組方法來克服現今應用軟體上的一些限制。由於我們也將記憶體的大小也列入模型的考量，所以我們提出的方法可以很有效的與記憶體產生器結合，根據不同大小的記憶體能自動調整我們的功率模型，而無需再對不同大小的記憶體再重新建立另一個功率模型。更凸顯出我們方法的實用性。
在處理器的電路區塊中，我們也提出了一套應用在指令層級的功率模型建構方法可應用在管線式超大指令字處理器。在我們的方法中，不論是各個指令的基本功率消耗還是兩道指令間所多出來的額外功率消耗都能被考慮進來。由於我們也考慮管線的效應，這使得我們在處理器上的功率預估能更接近實際的功率消耗行為。整個功率預估的流程主要可以分成兩階段：能量萃取階段及功率重組階段。從我們的實驗數據裡可得知，此功率模型可以有相當的準確度。

摘要(英)

Power dissipation of complex digital circuits is often estimated by using power modeling approaches. The usage of this kind of approaches does not require any detailed information of circuits. Therefore, it can be used to estimate the power dissipation of the circuits in very high abstract level. In current approaches, power-model based power estimation methods seem to be more suitable for SOC designs to quickly provide the corresponding power consumption for a given set of input vectors. However, there are still many difficulties to apply existing power models to SOC designs. In addition, a typical system often consists of many blocks with quite different properties, which require different approaches to build their power models. Therefore, in this dissertation, we focus on developing the corresponding high-level power modeling methodologies for each block in SOC designs. These IP blocks can be roughly classified into random logic blocks with combinational and sequential circuits, embedded memory blocks and processor blocks.
For random logic blocks with combinational and sequential circuits, we focus on developing a novel power modeling approach using neural network to estimate the power dissipation on high level. In our approach, the multi-layer feed-forward neural network is used for modeling combinational circuits and multi-layer recurrent neural network is used for sequential circuits. Experimental results on ISCAS’85, ISCAS’89 benchmark circuits and some real designs show that the developed power models achieve good accuracy 4.72% and 4.19% for both combinational and sequential circuits, respectively.
Embedded memories have been used extensively in modern SOC designs. In order to estimate the power consumption of the entire design correctly, an accurate memory power model is needed. However, the memory power model commonly used in commercial EDA tools is too simple to estimate the power consumption accurately. In this dissertation, we develop two methods to improve the accuracy of memory power estimation. Our enhanced memory power model can consider not only the operation mode of memory access, but also the address switching effects with scaling capability. The developed approach is very useful to be combined with the memory compiler to generate accurate power model for any specified memory size without extra characterization costs. Then the developed dummy modular approach can link our enhanced memory power model into the existing power estimation flow smoothly. The experimental results have shown that the average error of our memory power model is only less than 5%.
For micro-processor circuits, we develop a new instruction-level energy modeling approach for pipelined Very Large Instruction Word (VLIW) DSPs. The developed approach can take care of both the base energy cost of each instruction and the additional energy cost of consecutive instructions in each pipeline stage. Therefore, the power estimation can be much closer to the real pipelined behavior since the pipeline issue had been considered. The overall power estimation procedure can be separated into two phases: energy extraction phase and model re-construction phase. The experimental results have shown that the average error of our approach is less than 3% compared to gate-level power simulation.

關鍵字(中)

★ 高階功率模型
★ 高階功率預估
★ 系統晶片功率預估

關鍵字(英)

★ high level power model
★ high level power estimation
★ soc power estimation
★ IP power model

論文目次

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Power Sources of CMOS Designs 3
1.3 High-Level Power Estimation Techniques 5
1.3.1 High-Level Power Modeling for Random Logic Blocks 7
1.3.2 High-Level Power Modeling for Embedded Memory Blocks 8
1.3.3 High-Level Power Modeling for Processor Cores 10
1.4 Organization 12
Chapter 2 Power Modeling for Random Logic Blocks 13
2.1 Motivation 13
2.2 Background 14
2.2.1 Previous Works 14
2.2.2 Neural Network Architecture 17
2.2.3 Training Process 20
2.2.4 Evaluating the Accuracy of a Trained Neural Network 23
2.3 Power Model Construction with Neural Networks 24
2.3.1 Input Data Type 25
2.3.2 Number of Hidden Neurons 28
2.3.3 Design Training Sets 30
2.4 Experimental Results 31
2.5 Summary 38
Chapter 3 Power Modeling for Embedded Memory Blocks 39
3.1 Motivation 39
3.2 Background 40
3.2.1 Previous Works 40
3.2.2 Embedded Memory Architecture 41
3.3 Enhanced Memory Power Modeling Using LIB Format 41
3.3.1 Non-control Signals Effects 42
3.3.2 Dummy Modular Approach 44
3.3.3 Combine Our Model with Memory Compiler 46
3.4 Scalable Model Equations 48
3.4.1 Memory Core 49
3.4.2 Control Circuits 50
3.4.3 Column/Row Decoder 50
3.5 Experimental Results 52
3.6 Summary 54
Chapter 4 Power Modeling for Processor Cores 55
4.1 Motivation 55
4.2 Background 56
4.2.1 Previous Works 56
4.2.2 The Basic Approach of ILPA 57
4.2.3 Target VLIW DSP Core Architecture 58
4.3 The Proposed Instruction-Level Energy Model 59
4.3.1 ISA Clustering Rule 59
4.3.2 Profiling Method in the Pipelined Processor 60
4.3.3 Power Model Re-construction for VLIW DSP Cores 63
4.4 Experimental Results 65
4.5 Summary 67
Chapter 5 Conclusions and Future Works 68
References 70

參考文獻

[1] W. Nebel and J. Mermet, “Low Power Design in Deep Submicron Electronics,” Kluwer Academic Publishers, 1997.
[2] A. Salz, M. Horowitz, “IRSIM: An Incremental MOS Switch-Level Simulator,” in Proc. of ACM/IEEE on Design Automation Conference, pp. 173-178, 1989.
[3] A. C. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” in Proc. of International Workshop on Low Power Design, pp. 3-8, 1994.
[4] R. Burch, F. N. Najm, P. Yang and T. N. Trick, “A Monte Carlo Approach for Power Estimation,” IEEE Trans. on VLSI System, vol. 1, pp. 63-71, Mar. 1993.
[5] F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE trans. on VLSI Systems, vol. 2, pp. 446-455, Dec. 1994.
[6] P. Landman, “High-Level Power Estimation,” in Proc. of International Symp. on Low Power Electronics and Design, pp. 29-35, 1996.
[7] E. Macii, M. Pedram, F. Somenzi, “High-Level Power Modeling, Estimation, and Optimization,” IEEE Trans. on Computer-Aided Design, vol. 17, pp. 1061-1079, Aug. 1998.
[8] A. Raghunathan, N.K. Jha, S. Dey, “High-Level Power Analysis and Optimization,” Kluwer Academic Publishers, Boston/Dordrecht/London, 1998.
[9] M. Nemani and F. Najm, “Towards a High-Level Power Estimation Capabillity,” IEEE Trans. on Computer-Aided Design, vol. 15, pp. 588-598, Jun. 1996.
[10] D. Marculescu, R. Marculescu, and M. Pedram, “Information Theoretic Measures of Energy Consumption at Register Transfer Level,” in Proc. of ACM/IEEE Internal Symp. on Low Power Design, pp. 87-92, 1995.
[11] S. Gupta and F. N. Najm, “Power Modeling for High-Level Power Estimation,” IEEE Trans. on VLSI Systems, vol. 8, pp. 18-29, Feb. 2000.
[12] A. Bogliolo, R. Corgnati, E. Macii and M. Poncino, “Parameterized RTL Power Models for Soft Macros,” IEEE Trans. on VLSI Systems, vol. 9, pp. 880-887, Dec. 2001.
[13] C.-Y. Hsu, C.-N. Liu and J.-Y. Jou, “An Efficient IP-Level Power Model for Complex Digital Circuits,” in Proc. of Asia South Pacific Design Automation Conference, pp. 610-613, Jan. 2003.
[14] S. Gupta and F. N. Najm, “Analytical Models for RTL Power Estimation of Combinational and Sequential Circuits,” IEEE Trans. on Computer-Aided Design, vol. 19, pp. 808-814, Jul. 2000.
[15] Q. Wu, Q. Qiu, M. Pedram, and C.-S. Ding, “Cycle-Accurate Macro-Models for RT-Level Power Analysis,” IEEE Trans. on VLSI Systems, vol. 6, pp. 520-528, Dec. 1998.
[16] S. Gupta and F. N. Najm, “Energy-Per-Cycle Estimation at RTL,” in Proc. of ACM/IEEE Internal Symposium on Low Power Design, pp. 121-126, 1999.
[17] T. M. Cover and J. A. Thomas, “Elements of Information Theory,” A Wiley-Interscience publication, 1991.
[18] T. L. Fine, “Feedforward Neural Network Methodology,” New York: Springer, 1999.
[19] W.-T. Hsieh, C.-C. Yu, C.-N. Liu, and Y.-F. Chiu, " An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, pp. 1038-1044, May 2007.
[20] W.-T. Hsieh, C.-C. Yu, C.-N. Liu, and Y.-F. Chiu, "A Scalable Power Modeling Approach for Embedded Memory Using LIB Format," International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 543-552, Sep. 2006.
[21] C.-H. Chang and D. Marculescu, “Design and Analysis of a Low Power VLIW DSP Core,” Proc. of Emerging VLSI Technologies and Architectures, 2006.
[22] D. M. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva, A. Buyuktosunoglu, J. Wellman, V. Zyuban, M. Gupta and P. W. Cook, “Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors,” IEEE MICRO. vol.20, pp. 26-44, 2000.
[23] W. Ye, N. Vijaykrishnan, M. Kandemir and M. Irwin, “The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool,” in Proc. of Design Automation Conference, pp. 340-345, Jun. 2000.
[24] D. Brooks, V. Tiwari and M. Martonosi, “Wattch: a framework for architectural-level power analysis and optimizations,” in Proc. of International Symposium on Computer Architecture, pp.83-94, 2000.
[25] L. Cao, “Circuit Power Estimation Using Pattern Recognition Techniques,” IEEE/ACM International Conf. on Computer-Aided Design, pp. 412-417, 2002.
[26] W. T. Hsieh, “A Novel High-Level Power Model Using Neural Network,” Master Thesis, Dept. Elec. Eng., National Central University, Taiwan, Jun., 2003.
[27] C.-Y. Hsu, W.-T. Hsieh, C.-N. Liu, and J.-Y. Jou, " A Tableless Approach for High-Level Power Modeling Using Neural Networks,” Journal of Information Science and Engineering, vol. 23, pp.71-90, Jan. 2007.
[28] F. A.T. and O. A.L., “Implicit Resolution of the Chapman-Kolmogorov Equations for Sequential Circuits: An Application in Power Estimation,” Design, Automation and Test in Europe Conference and Exhibition, pp. 764-769, 2003.
[29] G. Hachtel, E. Macii, A. Pardo, and F. Somenzi. “Markovian Analysis of Large Finite State Machines,” IEEE Trans. on Computer-Aided Design, vol. 15, pp. 1479-1493, Dec. 1996.
[30] W.-T. Hsieh, C.-C. Shiue, and C.-N. Liu, "An Efficient Power Modeling Approach of Sequential Circuits Using Recurrent Neural Networks," IEE Proc. of Computers and Digital Techniques, vol. 153, pp. 78-86, Mar. 2006.
[31] W.-T. Hsieh, C.-C. Shiue and C.-N. Liu, “A Novel Approach for High-Level Power Modeling of Sequential Circuits Using Recurrent Neural Networks,” IEEE International Symp. on Circuits and Systems, pp. 3591-3594, 2005.
[32] J. L. Elman, “Finding Structure in Time,” Cognitive Science, vol. 14, pp. 179-211, 1990.
[33] K. Levenberg, “A Method for The Solution of Certain Problem in Least Square,” Quarterly of Applied Mathematics, vol. 11, pp. 164-168, 1944.
[34] D.W. Marquardt, “An algorithm for least squares estimation of non-linear parameters,” Journal of the Society for Industrial and Applied Math., vol. 11, pp. 431-441, 1963.
[35] G. Jochens, L. Kruse, W. Nebel,“ A New Parameterizable Power Macro-Model for Datapath Components,” in Proc. of European Design and Test Conference, pp. 29-36, 1999.
[36] K. Mehrotra, C. K. Mohan and S. Ranka, “Elements of Artificial Neural Networks,” Cambridge, Massachusetts: MIT Press, 1997.
[37] E. B. Baum and D. Haussler, “What Size Net Gives Valid Generalization?” Neural Computation, vol. 1, pp. 151-160, 1989.
[38] E. Boutillon, W.J. Gross, P.G. Gulak, “VLSI Architectures for The MAP Algorithm,” IEEE Trans. on Communications, vol. 51, pp. 175 -185, Feb. 2003.
[39] International Technology Roadmap for Semiconductors, http://www.itrs.net/.
[40] B. S. Amrutur, M. A. Horowitz, “Speed and Power Scaling of SRAM's,” IEEE Trans. on Solid-State Circuits, vol. 35, pp. 175 – 185, Feb. 2000.
[41] R. J. Evans, P. D. Franzon, “Energy Consumption Modeling and Optimization for SRAM's,” IEEE Trans. on Solid-State Circuits, vol. 30, pp. 571 – 579, May 1995.
[42] M. Chinosi, R. Zafalon, C. Guardiani, “Automatic Characterization and Modeling of Power Consumption in Static RAMs,” Low Power Electronics and Design, Aug. 1998.
[43] S. L. Coumeri, D. E. Thomas, Jr., “Memory Modeling for System Synthesis,” IEEE Trans. on VLSI Syst., vol. 8, pp. 327 – 334, Jun. 2000.
[44] E. Schmidt, G. v. Colln, L. Kruse, F. Theeuwen, W. Nebel, “Memory Power Models for Multilevel Power Estimation and Optimization,” IEEE Trans. on VLSI System, vol. 10, pp. 106-109, Apr. 2002.
[45] M. Mamidipaka, K. Khouri, N. Dutt and M. Abadir, “IDAP: A Tool for High-Level Power Estimation of Custom Array Structures,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1361-1369, Sep. 2004.
[46] M. Q. Do, M. Drazdziulis, P. L. Edefors and L. Bengtsson, “Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays,” International Symposium on Quality Electronic Design, pp. 185-191, Mar. 2007.
[47] G. Reinman and N. Jouppi, “CACTI 2.0: An Integrated Cache Timing and Power Model,” WRL Research Report 2000/7, Feb. 2000.
[48] S.Wilton and N. Jouppi, “An Enhanced Access and Cycle TimeModel for On-chip Caches,” WRL Research Report 93/5, Jun. 1994.
[49] “TSMC 0.25μm Process SRAM-SP-HD Generator User Manual,” Release 5.0, Artisan Comp., Jan. 2002.
[50] “Library Compiler User Guide: Modeling Timing and Power Technology Libraries,” Synopsys, Mar. 2003.
[51] J. Olson, I. Nedelchev, Y. Lin, A. Mauskar, and J. Sproch, “STATE DEPENDENT POWER MODELING,” US Patent # 5,838,579, 1998.
[52] S. Mittra, “Principles of Verilog PLI,” Kluwer Academic Publishers, Mar. 1999.
[53] “Nanosim User Guide: Version X-2005.09,” Synopsys, Sep. 2005.
[54] V. Tiwari, S. Malik and A. Wolfe, “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization,” IEEE Trans. on Very Large Scale Integration Systems, vol. 2, pp. 437-445, Dec. 1994.
[55] V. Tiwari, S. Malik, A. Wolfe and M.T.-C. Lee, “Instruction Level Power Analysis and Optimization of Software,” Int. Conf. on VLSI Design, pp. 326-328, 1996.
[56] M.T.-C. Lee, V. Tiwari, S. Malik and M. Fujita, “Power Analysis and Minimization Techniques for Embedded DSP Software,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 5, pp. 123-135, Mar. 1997.
[57] V. Tiwari and T.C. Lee, “Power Analysis of a 32-bit Embedded Microcontroller,” Int. Conf. on Asian and South Pacific Design Automation, pp. 141-148, 1998.
[58] J. T. Russel and M. F. Jacome, “Software Power Estimation And Optimization for High Performance 32-bit Embedded Processors,” Int. Conf. on Computer Design, pp. 328-333, 1998.
[59] D. Sarta, D. Trifone and G. Ascia, “A Data Dependent Approach to Instruction Level Power Estimation, ” IEEE Low Power Design Workshop, pp. 182-190, 1999.
[60] S. Nikolaidis, N. Kavvadias, T. Laopoulos, L. Bisdounis and S. Blionas, “Instruction Level Energy Modeling for Pipelined Processors,” Journal of Embedded Computing, vol. 1, pp. 317-324, 2005.
[61] M. Sami, D. Sciuto, C. Silvano and V. Zaccaria, “An Instruction-level Energy Model for Embedded VLIW Architectures,” IEEE Trans. on Computer-Aided Design, vol. 21, pp. 998-1010, Sep. 2002.
[62] J. L. Hennessy and D. A. Patterson, “Computer Architecture: A Quantitative Approach,” Morgan Kaufmann Publishing Co., 2007.
[63] V. Zaccaria, M. Sami, D. Sciuto and C. Silvano, “Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems,” Kluwer Academic Publishers, 2003.

指導教授

劉建男(Chien-Nan Liu)

審核日期

2007-7-19

推文