參考文獻 |
[1]J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[2]B. Razavi, “Design of Analog CMOS Integrated Circuit,” McGraw-Hill, New York, NY 2001.
[3]R. E. Best, Phase-Locked Loops: Design, Simulation, and Application, 3rd Edition. McGraw-Hill, New York, NY 1997.
[4]M. J. E. Lee, W. J. Dally, J. W. Poulton, P. Chiang, and S. F. Greenwood, “An 84-mW 4-Gb/s Clock and Data Recovery Circuit for Serial Link Applications,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 149-152, 2001.
[5]C. Y. Yang, “Design of Clock Synchronizers and Frequency Synthesizers”, Ph.D. thesis, Graduate Institute of Electronics Engineering, National Taiwan University, June 2000.
[6]G. Kim, M. K. Kim, B.S. Chang, and W. Kim, “A Low-Voltage, Low Power CMOS Delay Element,” IEEE J. Solid-State Circuits, vol. 31, pp. 966-971, July 1996.
[7]M.-J. E. Lee, W. J. Dally, T. Greer, H. T. Ng, R. Farjad-Rad, J. Poulton, and R. Senthinathan, “Jitter Transfer Characteristics of Delay-Locked Loops–Theories and Design Techniques,” IEEE J. Solid-State Circuits, vol. 38, pp. 614-621, Apr. 2003.
[8]J. W. Lin, “Design and Realization of Analog Delay-Locked Loops”, M.S. thesis, Graduate Institute of Electronics Engineering, National Taiwan University, June 2001.
[9]H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu,” A Wide-Range Delay-Locked Loop With a Fixed Latency of One Clock Cycle,” IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002.
[10]S. Wu and B. Razavi, “A 900-MHz/1.8-GHz CMOS Receive for Dual-Band Applications,” IEEE J. Solid-State Circuits, vol. 33, pp. 2178-2185, Dec. 1998.
[11]G. Hsieh and J. C. Hung, “Phase-Locked Loop Techniques-A Survey,” IEEE Transactions on Industrial Electronics, vol. 43, pp. 609-615, Dec. 1996.
[12]B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits. IEEE Press, Piscataway, NJ 1996.
[13]W. C. Lindsey, and M. K. Simon, Phase-Locked Loops & Their Application . IEEE Press, New York, NY 1977.
[14]J. L. Stensby, Phase-Locked Loops: Theory and Application. CRC Press, New York, NY 1977.
[15]J. Encinas, Phase Locked Loops. Chapman & Hall, London 1993.
[16]F. M. Gardner, “Charge-Pump Phase-Locked Loops,” IEEE Trans. Commun., vol. COM-28, pp.1849-1858, Nov. 1980.
[17] D. Johns and K. Martin, “Analog Integrated Circuit Design,” John Willey & Sons, New York, NY 1997.
[18]C. H. Park, and B. Kim, “A Low-Noise, 900-MHz VCO in 0.6-μm CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 586-591, May 1999.
[19]F. M. Gardner, “Phaselock Techniques,” 2rd Edition. New York: Wiley & Sons, 1979.
[20]K. H. Cheng, K. F. Chang, Y. L. Lo, C. W. Lai, and Y. K. Tseng, “A 100MHz-1GHz Adaptive Bandwidth Phase-Locked Loop in 90nm Process,” IEEE International Symposium on Circuits and Systems, pp. 3205-3208, May 2006.
[21]“An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLLs,” National Semiconductor Application Note, July 2001.
[22]Y. Tang, M. Ismail, and S. Bibyk, “Adaptive Miller Capacitor Multiplier for Compact On-Chip PLL Filter” Electron. Lett., vol. 39, pp. 43-45, Jan. 2003.
[23]Y. J. Jung, S. W. Lee, D. Shim, W. Kim, and S. I. Cho, “A Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines,” IEEE J. Solid-State Circuits, vol. 36, pp. 784-791, May 2001.
[24]D. J. Foley and M. P. Flynn, “CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,” IEEE J. Solid-State Circuits, vol. 36, pp. 417-423, Mar. 2001.
[25]Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,” IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
[26]K. H. Cheng, Y. L. Lo and S. Y. Jiang, “A Fast-Lock DLL with Power-On Reset Circuit,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol.E87-A, pp. 2210-2220, Sep. 2004.
[27]K. H. Cheng, W. B. Yang, and C. M. Ying, “A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 892-896, Nov. 2003.
[28]C. Y. Yang and S. I. Liu, “Fast-Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector,” IEEE J. Solid-State Circuits, vol. 35, pp. 1445-1452, Oct. 2000.
[29]T. Yasuda, M. Yamamoto, and T. Nishi, “A Power-On Reset Pulse Generator For Low Voltage Application,” IEEE International Symposium on Circuits and Systems, pp. 599-601, May 2001.
[30]I. A. Young, J. K. Greason, and K. L. Wong, “A PLL Clock Generator with 5 to 110MHz of Lock Range for Microprocessor,” IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
[31]H. O. Johansson, “A Simple Precharged CMOS Phase Frequency Detector,” IEEE J. Solid-State Circuits, vol. 33, pp. 295-299, Feb. 1998.
[32]H. Kondoh, H. Notani, T. Yoshimura, H. Shibata, and Y. Matsuda “A 1.5 V 250 MHz to 3.0V 622 MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector,” IEICE Trans. Electron, Vol.E78-C, pp. 381-388, Apr. 1995.
[33]K. H. Cheng, H. S. Liao, and L. J. Tzou, “A Low-Jitter and Low-Power Phase-Locked Loop Design,” IEEE International Symposium on Circuits and Systems, pp. 257-260, May 2000.
[34]W. Rhee, “Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops,” IEEE International Symposium on Circuits and Systems, pp. 545-548, May 1999.
[35]Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,” IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
[36]K. H. Cheng and Y. L. Lo, “A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency Range Selector for Multiphase Clock Generator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, pp. 561-565, July 2007.
[37]K. H. Cheng, S. M. Chang, Y. L. Lo, and S. Y. Jiang, “A 2.2 GHz Programmable DLL-Based Frequency Multiplier for SOC Applications,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 72-75, Aug. 2004.
[38]C. C. Chung and C. Y. Lee, “A New DLL-Based Approach for All-Digital Multiphase Clock Generation,” IEEE J. Solid-State Circuits, vol. 39, pp. 469-475, Mar. 2004.
[39]H. H. Chang, R. J. Yang, and S. I. Liu, “Low Jitter and Multirate Clock and Data Recovery Circuit Using a MSADLL for Chip-to-Chip Interconnection,” IEEE Trans. Circuits Syst. I, vol. 51, pp. 2356-2364, Dec. 2004.
[40]Q. Du, J. Zhuang, and T. Kwasniewski, “A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction,” IEEE Trans. Circuits Syst. II, vol. 53, pp. 1205-1209, Nov. 2006.
[41]R. Farjad-Rad, W. Dally, H. T. Ng, R. Senthinathan, M. J. E. Lee, R. Rathi, and J. Poulton, “A Low-Power Multiplier DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips,” IEEE J. Solid-State Circuits, vol. 37, pp. 1804-1812, Dec. 2002.
[42]P. Chen, S. I. Liu, and J. Wu, “A CMOS Pulse-Shrinking Delay Element For Time Interval Measurement,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 954-958, Sep. 2000.
[43]K. H. Cheng, C. W. Lai, and Y. L. Lo, “A CMOS VCO for 1V, 1GHz PLL Applications,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 150-153, Aug. 2004.
[44]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg, and P. T. Balsara, “1.3 V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS,” IEEE Trans. Circuits Syst. II, vol. 53, pp. 220-224, Mar. 2006.
[45]W. B. Wilson, U. K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS Self-Calibrating Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 35, pp. 1437-1444, Oct. 2000.
[46]J. Kim, M. A. Horowitz, and G. Y. Wei, “Design of CMOS Adaptive-Bandwidth PLL/DLLs: A General Approach,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 860-869, Nov. 2003.
[47]S. Sidiropoulous, D. Liu, J. Kim, G. Y. Wei, and M. A. Horowitz, “Adaptive Bandwidth DLLs and PLLs Using Regulated Supply CMOS Buffers,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 124-127, Jun. 2000.
[48]S. Kim, K. Lee, Y. Moon, D. K. Jeong, Y. Choi, and H. K. Kim, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997.
[49]J. Yuan and C. Svensson, “Fast CMOS Nonbinary Divider and Counter,” Electron. Lett., vol. 29, pp. 1222-1223, June 1993.
[50]S. H. Lee and H. J. Park, “A CMOS High-Speed Wide-Range Programmable Counter,” IEEE Trans. Circuits Syst. II, vol. 49, pp. 638-642, Sep. 2002.
[51]H. H. Chang and J. C. Wu, “A 723-MHz 17.2-mW CMOS Programmable Counter,” IEEE J. Solid-State Circuits, vol. 33, pp. 1572-1575, Oct. 1998.
[52]M. A. Do, X. P. Yu, J. G. Ma, K. S. Yeo, R.Wu, and Q. X. Zhang, “GHz programmable counter with low power consumption,” Electron. Lett., vol. 39, pp. 1572-1573, Oct. 2003.
[53]X. P. Yu, M. A. Do, L. Jia, J. G. Ma, and K. S. Yeo, “Design of a Low Power Wide-Band High Resolution Programmable Frequency Divider,” IEEE Trans. Very Large Scale Integr. Syst., vol. 13, pp. 1098-1103, Sep. 2005.
[54]S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Frequency Divider,” IEEE J. Solid-State Circuits, vol. 39, pp. 378-383, Feb. 2004.
[55]B. Chang, J. Park, and W. Kim, “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.
[56]J. Navarro and W. Van Noije, “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” IEEE J. Solid-State Circuits, vol. 34, pp. 97-102, Jan. 1999.
[57]C. Y. Yang, G. K. Dehng, and S. I. Liu, “New Dynamic Flip-Flop for High-Speed Dual-Modulus Prescaler,” IEEE J. Solid-State Circuits, vol. 33, pp. 1568-1571, Oct. 1998.
[58]J. M. Hsu, G. K. Dehng, C. Y. Yang, C. Y. Yang, and S. I. Liu, “Low-Voltage CMOS Frequency Synthesizer for ERMES Pager Application,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 826-834, Sep. 2001.
[59]R. S. Rana, “Dual-Modulus 127/128 FOM Enhanced Prescaler Design in 0.35-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 40, pp. 1662-1670, Aug. 2005.
[60]J. Yuan and C. Svensson, “High Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
[61]M. Afghahi and C. Svensson, “A Unified Single-Phase Clocking Scheme for VLSI Systems,” IEEE J. Solid-State Circuits, vol. 25, pp. 225-235, Feb. 1990.
[62]S. H. Yang, Y. You, and K. R. Cho, “A New Dynamic D-Flip-Flop Aiming at Glitch and Charge Sharing Free,” IEICE Trans. on Electron, Vol.E86-C, pp. 496-504, Mar. 2004.
[63]C. Y. Yang, G. K. Dehng, and S. I. Liu, “High-Speed Divide-by-4/5 Counter for a Dual-Modulus Prescaler,” Electron. Lett., vol. 33, pp. 1691-1692, Sep. 1997.
[64]S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V Analog Circuit Techniques and Their Application in OTA and Filter Design,” IEEE J. Solid-State Circuits, vol. 40, pp. 2373-2387, Dec. 2005.
[65]K. Arnim, E. Borinski, P. Seegebrecht, H. Fiedler, R. Brederlow, R. Thewes, J. Berthold, and C. Pacha, “Efficiency of Body Biasing in 90-nm CMOS for Low-Power Digital Circuits,” IEEE J. Solid-State Circuits, vol. 40, pp. 1549-1556, Jul. 2005.
[66]S. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel, S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar, A. Keshavarzi, V. Erraguntla, G. Dermer, N. Borkar, S. Borkar, and V. De, “Ultra-Low Voltage Circuits and Processor in 180nm to 90nm Technologies with a Swapped-Body Biasing Technique,” ISSCC Dig. Tech. Pepers, pp. 156-157, Feb. 2004.
[67]H. H. Hsieh, C. T. Lu, and L. H. Lu, “A 0.5-V 1.9-GHz Low-Power Phase-Locked Loop in 0.18-μm CMOS,” IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 164-165, Jun. 2007.
[68]B. Blalock, P. Allen, and G. Rincon-Mora, “Designing 1-V Op Amps Using Standard Digital CMOS Technology,” IEEE Trans. Circuits Syst. II, vol. 45, pp. 769-780, Jul. 1998.
[69]S. S. Rajput and S. S. Jamuar, “Design Techniques for Low Voltage Analog Circuit Structures,” NSM 2001/IEEE, Malaysia, Nov. 2001.
[70]G. Giustolisi, G. Palumbo, M. Criscione, and F. Cutrì, “A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETs,” IEEE J. Solid-State Circuits, vol. 38, pp. 151-154, Jan. 2003.
[71]J. Ramirez-Angulo, S. C. Choi, and G. G. Altamirano, “Low Voltage Circuits Building Blocks Using Multiple Input Floating Gate Transistors,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 971-974 Nov. 1995.
[72]P. Hasler, and T. S. Lande, “Overview of Floating Gate Devices, Circuits and Systems,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 1-3, Jan. 2001.
[73]S. Yan and E. Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial”, IEICE Transactions on Fundamentals, vol. E83-A, Feb. 2000.
[74]S. Karthikeyan, S. Mortezapour, A. Tammineedi, and E. Lee, “Low-Voltage Analog Circuit Design Based on Biased Inverting Opamp Configuration,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 176-184, Mar. 2000.
[75]K. Langen and J. H. Huijsing, “Compact Low-Voltage Power Efficient Operational Amplifier Cells for VLSI”, IEEE J. Solid-State Circuits, vol. 33, pp. 1483-1496, Oct. 1998.
[76]M. Kokubo, T. Kawamoto, T. Oshima, T. Noto, M. Suzuki, S. Suzuki, T. Hayasaka, T. Takahashi, and J. Kasai, “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” ISSCC Dig. Tech. Pepers, pp. 160-590, Feb. 2005.
[77]J. Nakanishi, H. Notani, H. Makino, and H. Shinohara, “A Wide Lock-in Range PLL using Self-Calibrating Technique for Processors, ” IEEE Asian Solid-State Circuits Conference, pp. 285-288, Nov. 2005.
[78]T. H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE J. Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001.
[79]H. R. Lee, M. S. Hwang, B. J. Lee, Y. D. Kim, D. Oh, J. Kim, S. H. Lee, D. K. Jeong, and W. Kim, “A 1.2-V-Only 900-mW 10 Gb Ethernet Transceiver and XAUI Interface With Robust VCO Tuning Technique,” IEEE J. Solid-State Circuits, vol. 40, pp. 2148-2158, Nov. 2005.
[80]T. H. Lin and Y. J. Lai, “An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL,” IEEE J. Solid-State Circuits, vol. 42, pp. 340-349, Feb. 2007. |