標準元件庫雜訊特性化及電源雜訊抑制電路設計

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姓名

杜明賢(Ming-Hsien Tu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

標準元件庫雜訊特性化及電源雜訊抑制電路設計
(Standard Cell Library Noise Characterization and Power Noise Suppression Circuit Design)

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摘要(中)

摘要
隨著半導體製造技術的進步，最小特徵尺寸持續降低，而且電路密度逐漸增加。在這個同時，增加的時脈速度要求這些電路有更快的訊號轉換速率。如此，在今天的高速電路中，雜訊產生變得愈來愈嚴重。然而，供應電源電壓的減少代表著更低的電晶體臨界電壓。因此，電路的雜訊邊界變得更小。它會造成大量的訊雜比降低，不管是在數位或是混合訊號電路。因此，電路效能將被雜訊所限制。
在這個論文，我們提供一個能察覺雜訊的標準元件庫。有兩個主要的部份在這個目標，雜訊特性化與抑制雜訊元件設計。在雜訊特性化方面，我們介紹特性化交插耦合雜訊的程序與使用CLKINVX1與NAND2X1來當成特性化例子。我們也討論特性化同時轉換雜訊的方法與呈現一些初步的想法。
在雜訊抑制元件設計方面，我們實現了被動抑制電源雜訊元件，去耦合電容，與一個主動抑制電源雜訊模組。它們可以直接抑制在設計者電路中所發生的電源雜訊。模擬結果顯示，主動抑制電源電路能降低負的電源雜訊峰值達33%，降低正的電源雜訊峰值達44%。最後我們將主動抑制電源雜訊電路與晶片上抖動量測電路做結合。這個結合電路可以讓我們直接觀察主動抑制電源雜訊電路所造成的改善。

摘要(英)

Abstract
With advances in semiconductor fabrication technology, the minimum feature size continues to decrease and the circuit density increases gradually. At the same time, increasing clock speeds demands these circuits to switch at faster rates. Thus, noise generation becomes more and more serious in today’s high-speed circuits. Moreover, decreasing power supply voltages dictate lower transistor threshold voltage. Therefore, noise margins of circuits become smaller. It causes a significantly signal-to-noise ratio reduction for both digital and mixed-signal/analog circuits. Therefore, the circuit performance will be limited by noise.
In this thesis, we provide a noise-aware standard cell library. There are two major parts in the subject, noise characterization and noise suppression cell design. On noise characterization, we introduce the procedure to characterize the noise behavior and use CLKINVX1 and NAND2X1 as a characterization example. We also discuss the way to characterize simultaneous switching noise and propose some preliminary ideas.
On noise suppression cell design, we implement the passive power supply noise (PSN) suppression cell, decoupling capacitance, and an active PSN suppression module. They can be used to suppress PSN occurring in design’s circuit. The simulation results appeal that the active PSN suppression circuit can have 33% reduction for negative PSN peak and 44% reduction for positive PSN peak. Finally, we combine the active PSN suppression circuit with an on-chip bounce measurement circuit. This combined circuit can let us observe the improvement due to the active PSN suppression circuit directly.

關鍵字(中)

★ 標準元件庫
★ 雜訊
★ 特性化

關鍵字(英)

★ characterization
★ standard cell library
★ noise

論文目次

Contents
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Introduction 2
1.2.1 Standard Cell Library 2
1.2.2 Noise Characterization 3
1.2.3 Low-Noise Cells and Anti-Noise Modules 4
1.2.4 On-Chip measurement Circuit 5
1.3 Thesis Organization 6
Chapter 2 Cross-Coupling Noise Model and Characterization Flow 7
2.1 Introduction to Cross-Coupling Noise 7
2.2 Cross-Coupling Noise Model in Liberty Format 9
2.2.1 Noise Calculation 10
2.2.2 Noise Immunity 10
2.2.3 Noise Propagation 12
2.3 Cross-Coupling Noise Characterization 13
2.3.1 Cross-Coupling Noise Characterization Flow 13
2.3.2 Generation of Cross-Coupling Noise Glitches 14
2.3.3 Weibull Function 15
2.3.4 Noise Calculation Characterization 23
2.3.5 Noise Immunity Characterization 27
2.3.6 Noise Propagation Characterization 31
2.4 Summary 33
Chapter 3 Simultaneous Switching Noise Model and Characterization 34
3.1 Introduce to Simultaneous Switching Noise 34
3.1.1 Causes of Simultaneous Switching Noise 34
3.1.2 Bounce Behavior of SSN 36
3.1.3 Negative Feedback 39
3.2 Power Supply Noise Estimation Methods 40
3.2.1 Dynamic Estimation Method 41
3.2.2 Static Estimation Method 42
3.2.3 Current Waveform Characterization 45
3.3 The Effects of SSN on Propagation Delay 49
3.3.1 Propagation Delay 49
3.3.2 The characteristics of a SSN Waveform 50
3.3.3 The Characterization of Tp 52
3.4 Summary 54
Chapter 4 Noise-Aware Cell Library 55
4.1 Cross-Coupling Noise and SSN Suppression Methods 55
4.1.1 Cross-Coupling Noise Suppression Methods 55
4.1.2 SSN Suppression Methods 57
4.2 Cell Adjustment for SSN Suppression 59
4.2.1 Sizing Experiment 59
4.2.2 Mixed-Vt Experiment 62
4.3 Coupling Noise Characterization Example 65
4.3.1 Noise Calculation － I-V Curve 65
4.3.2 Noise Propagation 71
4.3.3 Noise Immunity 76
4.4 Passive PSN Suppression Cell － Decoupling Capacitance 80
4.5 Active PSN Suppression Module Design 84
4.5.1 Background and Related Researches 84
4.5.2 Active PSN Suppression Circuit 87
4.5.3 Design and Simulation Results 92
4.5.4 Combine with On-Chip Measurement Circuit 96
4.6 Summary 100
Chapter 5 Conclusions 101
References 103
Appendix A – The Complete Cross-Coupling Noise Characterization Example of CLKINVX1 and NAND2X1 105

參考文獻

References
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指導教授

周世傑、劉建男
(Shyh-Jye Jou、Chien-Nan Liu)

審核日期

2006-7-11

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