地面與手持數位電視廣播同步迴路之設計與實現及低功率技術

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曾琪耀(Chi-Yao Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

地面與手持數位電視廣播同步迴路之設計與實現及低功率技術
(Design and Implementation of DVB-T/H Synchronization Loop and Low Power Techniques)

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摘要(中)

低功率設計一直是晶片設計的重要課題，尤其是愈來愈普及的可攜式電子裝置之使用時間受限於電池的有限載荷量。手持式數位電視廣播(DVB-H)利用時間切割技術來降低移動式接收機之功率消耗。在本論文中，我們著重於暫存器轉換層次的低功率設計技術之討論。我們的團隊分別針對架構和系統的低功率和低晶片面積觀點來設計此DVB-T/H基頻內接收機。我們採用一些低功率及功率察覺(power-aware)的設計以降低我們的DVB-T/H基頻內接收機的功率消耗。這些技術包含有預先計算、時脈閘控、運算元隔離、差值編碼、硬體共享、記憶體之分時多工讀寫、低功率算術運算架構以及功率管理者。最後，我們使用標準單元設計流程來實現此基頻內接收機。此基頻內接收機的架構包含有快速富利葉轉換(FFT)、前處理器(差分器、反旋轉器、彈性緩衝區、相位累加器)、後處理器(粗略符碼同步、散佈領航碼同步、通道估測)、快速富利葉轉換後估測(整數載波頻率誤差估測、餘數載波頻率誤差/取樣時脈誤差估測)。針對快速富利葉轉換後估測的部份(亦即同步迴路)，我們降低了51.6 %的晶片面積以及53.3 %的功率消耗。此外，我們所提出的功率管理者依照不同的保護區間長度，降低系統在誤差追蹤模式3% ~ 20%之功率消耗。

摘要(英)

Low power design is still an important issue of IC design; in particular, the popularizing portable electronic devices are time-limited used because of the finite energy capacity of battery. Digital Video Broadcasting for Handheld (DVB-H) introduces the time-slicing technique to decrease the power consumption of mobile receiver. In this thesis, we focus on the discussion about the register transfer level (RTL) low power design techniques. And our team designs the DVB-T/H baseband inner receiver with the low power and low area consideration in respect of architecture and system level. We utilize several low power and power aware design techniques to reduce the power consumption of our DVB-T/H baseband inner receiver. These techniques include pre-computation, clock gating, operand isolation, differential encoding, hardware sharing, time-multiplexing R/W of memory, low power arithmetic architecture and power manager. At last, we use the cell based design flow to implement our baseband inner receiver. The architecture of baseband inner receiver consists of FFT, Pre-processor (Interpolator, Derotator, elastic buffer and phase accumulator), Post-processor (Coarse Symbol Synchronization, Scattered Pilot Synchronization and Channel Estimation) and Post-FFT estimation (ICFO estimation and RCFO/SCO estimation). For the Post-FFT estimation (that is, synchronization loop), the area is reduced 51.6% and the power consumption is reduced 53.3%. Moreover, the proposed power manager reduces 3% ~ 20% power consumption according to different Guard Interval (GI) when the system is operating during the offset tracking mode.

關鍵字(中)

★ 低功率技術
★ 同步迴路
★ 數位電視廣播

關鍵字(英)

★ Low Power Technique
★ Synchronization Loop
★ Digital Video Broadcasting

論文目次

Chapter 1 Introduction 1
1.1 Overview of DVB-T System 1
1.2 Power Consumption in CMOS Circuit 4
1.3 Motivation 5
1.4 Thesis Organization 6
Chapter 2 RTL Low Power Design Techniques 7
2.1 Basic RTL Low Power Design 7
2.1.1 Precomputation 9
2.1.2 Clock Gating 10
2.1.3 Guarded Evaluation 11
2.1.4 FSM State Encoding 12
2.1.5 FSM Decomposition 13
2.1.6 Bus Encoding 14
2.1.7 Retiming 15
2.1.8 Parallel Architecture 16
2.1.9 Pipeline Architecture 17
2.2 Low Power Arithmetic 18
2.2.1 Signed-magnitude 19
2.2.2 LNS (Logarithmic Number System) 19
2.2.3 RNS (Residue Number System) 19
2.2.4 RLNS (Residue Logarithmic Number System) 19
2.3 On-Chip Memory 20
2.3.1 Hierarchical Memory and Computation Transformation 20
2.3.2 Memory Partitioning 22
2.4 Low Power Techniques in CAD Tool 22
2.4.1 Using DesignWare of SYNOPSYS 23
2.4.2 Clock Gating 25
2.4.3 Operand Isolation 26
2.4.4 Gate-level Power Optimization 28
Chapter 3 Power-Aware Design Techniques 31
3.1 Power-Aware Communication System 33
3.1.1 Energy Consumption of Electronic and RF in Radios 33
3.1.2 Dynamic Power Management (DPM) of Radios 34
3.2 Reconfigurable Processors 36
3.3 System-Level Dynamic Power Management 37
3.4 Dynamic Voltage Frequency Scaling System 39
3.5 Leakage Power Optimization Techniques 41
3.6 Multiple Vdd and Vth Low Power Design 44
Chapter 4 Hardware Design and Implementation of Post-FFT Synchronization Loop 46
4.1 Overview of DVB-T/H Baseband Inner Receiver 46
4.2 Timing Recovery Loop 49
4.2.1 SCO Estimation 49
4.2.2 Loop Filter 58
4.2.3 Interpolator Controller 59
4.2.4 Interpolator 61
4.2.5 Elastic Buffer 64
4.3 Carrier Frequency Recovery Loop 66
4.3.1 ICFO and FCFO Estimation 66
4.3.2 RCFO Estimation 68
4.3.2 Derotator 70
4.4 Dynamic Power Manager (DPM) 70
4.5 Summary of Low Power Design 77
Chapter 5 Implementation Result of DVB-T/H Baseband Inner Receiver 81
5.1 Chip Implementation Result 82
5.2 Measurement Consideration 85
5.2.1 Test of Specific Function 85
5.2.2 Design-for-Test with Scan Chain 86
Chapter 6 Conclusion and Future Work 87
Reference 89

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指導教授

蔡宗漢、周世傑
(Tsung-Han Tsai、Shyh-Jye Jou)

審核日期

2006-10-17

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