| 摘要(英) |
With the development of semiconductor technology, the verification process becomes quite difficult. Especially for modern complex designs, we often require a huge number of input patterns to verify the complex system behaviors. In this situation, although software simulation can provide full controllability and observability during the verification process, the simulation speed is too slow. Therefore, hardware emulation such as FPGA is more popular to gain high simulation speed. However, it is very hard to debug due to the poor visibility of internal nodes.
In order to solve this problem, “Snapshot Method” was proposed in [3]. It “records” the internal behaviors of FPGA and “replays” those behaviors in our interesting period in software simulator. In this kind of approaches, we can have full observability with high simulation speed during the verification process. However, the limitation of this approach is the limited resources on FPGA especially for the large designs which have include a lot of memory device.
Therefore, we propose a method to reduce the hardware overhead for the snapshot approach in this thesis. The experimental results have shown the efficiency of using our approach. |
| 參考文獻 |
[1] Signal Tap II embedded Logic Analyzer, Altera Corporation, http://www.altera.com/products/software/pld/design/verification/signaltap2/sig-index.html
[2] Chip Scope On Chip Debug Logic Analyzer, Xilinx Corporation, http://www.xilinx.com/ise/optional_prod/cspro.htm
[3] Chin-Lung Chuang; Dong-Jung Lu; Liu, D.-N.J., “A snapshot method to provide full visibility for functional debugging using FPGA”, in Proc. 13th Asia Test Symposium, Nov. 2004.
[4] International Technology Roadmap for Semiconductors, http://www.itrs.net/Common/2005ITRS/Test2005.pdf
[5] Value Change Dump File for Design Verification, http://www.mathworks.com/access/helpdesk/help/toolbox/modelsim/a1064428016.html
[6] Wei-Hsiang Cheng, Chih-Lung Chuang, and Chien-Nan Jimmy Liu, “An Efficient Mechanism to Provide Full Visibility for Hardware Debugging”, accepted to appear in IEEE International Symposium on Circuit and Systems, May 2006.
[7] 3.3V CMOS Static RAM 1 Meg （64K x 16-Bit）, 71V016SA datasheet, http://www.datasheetcatalog.com/datasheets_pdf/7/1/V/0/71V016SA.shtml
[8] Altera Corporation, Nios Development Board_APEX Edition, EP20K200EFC484-2X, http://www.altera.com
[9] Anurag Tiwari, Karen A. Tomko, “Scan-chain Based Watch-points for Efficient Run-Time Debugging and Verification of FPGA Designs”, ASPDAC, 2003.
[10] Logic Analyzer Interface, http://www.altera.com/products/software/products/quartus2/verification/lai/lai-index.html
[11] Joshua Marantz, “Enhanced Visibility and Performance in Functional Verification by Reconstruction”, Proc. DAC’98, San Francisco, CA
[12] Verisity Corporation, Xcite Simulation Acceleration platform, http://www.veridity.com/products/xcite.html
[13] Altera Corporation, Quartus II Design Software for Altera FPGAs, http://www.altera.com/literature/manual/intro_to_quartus2.pdf
[14] Model Technology Corporation, ModelSim SE 6.0, Simulation Software, http://www.model.com/products/se.asp |
[Endnote RIS 格式]
[相關文章]
[文章引用]
[完整記錄]
[館藏目錄]
[檢視]
plurk
funp
live
udn
HD
myshare
netvibes
friend
youpush
delicious
baidu
Google bookmarks
del.icio.us
hemidemi
facebook
twitter
google
reddit