摘要(英) |
With the development of semiconductor technology, the verification process becomes quite difficult. Especially for modern complex designs, we often require a huge number of input patterns to verify the complex system behaviors. In this situation, although software simulation can provide full controllability and observability during the verification process, the simulation speed is too slow. Therefore, hardware emulation such as FPGA is more popular to gain high simulation speed. However, it is very hard to debug due to the poor visibility of internal nodes.
In order to solve this problem, “Snapshot Method” was proposed in [3]. It “records” the internal behaviors of FPGA and “replays” those behaviors in our interesting period in software simulator. In this kind of approaches, we can have full observability with high simulation speed during the verification process. However, the limitation of this approach is the limited resources on FPGA especially for the large designs which have include a lot of memory device.
Therefore, we propose a method to reduce the hardware overhead for the snapshot approach in this thesis. The experimental results have shown the efficiency of using our approach. |
參考文獻 |
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