適用於MPEG-2/4 AAC編碼器的低複雜度MDCT-based聲學模型協同處理器設計與VLSI實現

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姓名

羅嘉和(Jia-Her Luo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於MPEG-2/4 AAC編碼器的低複雜度MDCT-based聲學模型協同處理器設計與VLSI實現
(Design and VLSI Implementation of Low Complexity MDCT-based Psychoacoustic-Model Co-Processor for MPEG-2/4 AAC Encoder)

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摘要(中)

音訊編碼的技術是我們生活中重要的一個部份，每一天人們從廣播、iPod、和手機中聽著他們喜愛的歌曲，而自從MP3風糜了全世界以後，MPEG組織在音訊編碼的技術上又推出新MPEG-2/4 AAC，來當成下一代新的音訊壓縮標準
在本篇論文中，我們最主要針對MPEG-2/4 AAC編碼器中之關鍵的元件設計，使得整個MPEG-2/4編碼器可以用在可攜式的電子產品。
聲學模型 Psychoacoustic Model (PAM)在MPEG-2/4編碼器扮演著一個非常重要的角色，由於他的運算複雜度相當的高使得它實現在低功率且要求即時編碼的可攜性的電子產品上仍有一定的難度，為了克服這一個問題，我們提出了一個專門加速聲學模型運算的協同處理器，在演算法上，我們使用以MDCT-based的聲學模型、將spreading function用查表的方式和以對數為基礎的資料來計算聲學模型的運算式以達到減少運算量和複雜的運算元，我們並且提出了以對數為基礎來運算Quantization Loop(Q Loop)中的運算以減少了PAM和Q Loop中的刻度轉換所須的複雜運算並簡化Q Loop中乘法和除法的運算;在架構上，我們用一個pipelining的MDCT與DSP-like的架構來計算整個PAM，本論文之架構以台積電0.18 CMOS製程實現，總共使用了28349個邏輯閘，整個設計能與一個MOPS低於7的DSP和ARM來即時編碼MPEG-2/4 AAC音訊資料。

摘要(英)

Audio technology is an important part in our life. Everyday, people listen to their favorite songs from broadcast、iPod、cellular phone…etc. After the MP3 very popular in the world, the MPEG organization proposed MPEG-2/4 AAC to be the next generation audio standard. In this thesis, we will present the key component design for MPEG-2/4 encoder of the portable device.
Psychoacoustic Model (PAM) as the key component in the MPEG-2/4 AAC encoder. It occupies the heavy computation load in AAC encoder and makes the AAC encoder hard to be implemented on the portable device under the real-time and low power condition. In order to overcome the above described problem, we proposed a dedicated co-processor design to speedup computation of the PAM. In algorithm level, the MDCT-based PAM、the look-up table of the spreading function ,the log-scale table of the Threshold Generator (TG) calculation are adopt to this design. Besides, logarithmic based Quantization Loop (Q Loop) algorithm is proposed to solve the scale and complexity computation problem between PAM and Q Loop. In architecture level, the pipelined MDCT and DSP-like architecture are proposed for the high efficient and low complexity consideration, respectively. The proposed PAM architecture is implemented in the TSMC 0.18 CMOS technology, total gate count is 28349. The proposed architecture can encoding stereo content with the DSP or the RISC, whose MOPS below 7 MOPS at sampling rate 44.1k and bitrate 128kbit/s.

關鍵字(中)

★ 先進編碼器
★ 聲學模型
★ MPEG

關鍵字(英)

★ Advanced Audio coding
★ Psychoacoustic-Model
★ MPEG

論文目次

Content..................................................................ii
List of Figures..........................................................iv
List of Tables...........................................................vi
Chapter 1 Introduction...............................................1
1.1 Brief history and feature of MPEG audio standards..........1
1.2 The MPEG-2/4 AAC Encoding System...........................4
1.3 Recent Developments: HE-AAC v1 Encoding System.............5
1.4 Recent Developments: HE-AAC v2 Encoding System.............6
1.5 Motivation.................................................7
1.6 Thesis Organization........................................8
Chapter 2 THE Fundamentals of MPEG-2/4 AAC Encoder.................11
2.1 Psychoacoustic Model......................................14
2.2 Modified Discrete Cosine Transform........................19
2.2.1 Window Shape Adaptation.........................................20
2.2.2 Block Type Decision.............................................20
2.3 Temporal Noise Shaping....................................22
2.4 Joint Stereo Coding.......................................22
2.5 Quantization Loop.........................................23
Chapter 3 Low Complexity PAM Algorithm and The Logarithmic Based
Q Loop...................................................26
3.1 MDCT-Based PAM............................................26
3.2 The Logarithmic-Based Q Loop Algorithm....................30
Chapter 4 The Architecture of The Low Complexity Psychoacoustic
Model....................................................32
4.1 Architecture of Input Buffer..............................34
4.2 Design of MDCT............................................35
4.2.1 The Algorithm of MDCT...........................................35
4.2.2 The Architecture of MDCT........................................37
4.3 Design of TG..............................................39
4.4 Low power and Low Area Logarithmic Hardware...............42
4.3.1 48-bit Leading-One Detector.....................................43
4.3.2 Algorithm and Circuit of 6-Region Compensation Circuit..........46
Chapter 5 Implementation and Result................................49
5.1 Test Coverage.............................................50
5.2 Comparisons...............................................51
5.3 Chip Layout and Summary...................................53
Chapter 6 Conclusions..............................................54
References...............................................................56

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2006-7-20

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