由於系統晶片設計的複雜度提高，元件之間的訊號交換電路已經變成功率消耗的一個主要來源。此研究中，我們提出一個有效率的高階功率模型，適用於前瞻微控制器匯流排架構(AMBA)協定所建構的晶片上完整通訊架構，每一個匯流排元件的功率模型會根據不同特性而用不同的方法去建立，仲裁器的功率模型使用查表的方式建立，解碼器和一些多工器採用以方程式為基礎的方式去建立，至於高效能匯流排和低功率匯流排之間橋梁的部分，我們則使用遞迴式類神經網路去學習功率的特徵值。除了建立功率模型之外，我們建好的功率模型還可以進一步整合到暫存器轉移階層的模擬器中，使得功率模擬的工作可在高階環境下便利地進行。最後實驗結果顯示，即使在各式各樣不同的測試平台下，我們提出的功率模型仍然可以達到週期精確的估測結果。 The communication architecture has become a major source of power consumption for complex System-on-Chip (SoC) design. In this work, we propose an efficient high-level power model for entire on-chip communication architecture using AMBA protocol. The power model of each bus component is created by different methods according to their distinct properties. Look-Up Table method is chosen to construct the power model of arbiter. Equation-based method is adopted in the decoder and some multiplexers. Elman Recurrent Neural Networks are used to learn the power characteristics in the APBif. In addition, our power model can be integrated into RTL simulator to facilitate the power simulation at high-level. The experimental results have shown that the proposed power model can achieve cycle-accurate estimation even for various test benches.
