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    题名: Ka頻段之交錯耦合雙推式壓控振盪器;A Ka-Band Cross-Coupled Push-Push VCO
    作者: 陳博軒;Po-Hsuan Chen
    贡献者: 電機工程研究所
    关键词: 雙推式;壓控振盪器;交錯耦合;push-push;cross-coupled;Ka-band;VCO
    日期: 2007-06-29
    上传时间: 2009-09-22 12:06:56 (UTC+8)
    出版者: 國立中央大學圖書館
    摘要: 本論文第一部份是利用單石微波積體電路(MMIC’s)來製作Ka-頻段交錯耦合雙推式壓控振盪器,其電路的實現乃利用穩懋半導體公司(WIN) 0.15 um InGaAs pHEMT 製程技術。在此電路中之被動元件的設計是採用微帶線(Microstrip line)來取代,以進行電路之匹配與偏壓電路設計,並利用交錯耦合對(cross-coupled pair)的方式來產生一負電阻以達到振盪,而共振腔的可變電容是利用pHEMT電晶體的接面操作在逆向偏壓下所得之接面電容所實現。電路特性表現方面,其量測結果在44 mW的功率消耗下,振盪頻率在30.07 GHz有輸出功率 -6.9 dBm,而相位雜訊在偏移中心頻率1 MHz時為 -95.81 dBc/Hz,以及在調變電壓為0.2 ~ 1.5 V的調整下,有69 MHz的調諧範圍,F.O.M為-168.94 dBc/Hz。 第二部份則是利用負載推移(Load-pull)系統之調諧器(Tuner)來改變壓控振盪器電路之負載阻抗,以觀察其對輸出功率的影響,量測結果發現在 , 的調整範圍下,最大之輸出功率是在ΓL = 0.5∠0的位置,其值為 -3 dBm左右,最小之輸出功率在ΓL =0.5 ∠2π/3的位置,其值為 -13 dBm左右,而ΓL = 0之輸出功率則為 -7 dBm左右。 附錄中是介紹一新穎的共平面波導佈局 (CPW Layout) 設計來應用於交錯耦合式壓控振盪器中,使得電路在交錯耦合的位置不會有重疊發生,可避免一些在高頻之下的耦合效應。 In this thesis, the Ka-band cross-coupled push-push Voltage Controled Oscillator (VCO) in WIN Semiconductor 0.15-μm pseudomorphic High Electron Mobility Transistor (pHEMT) technology is presented. The passive devices in this circuit are displaced by the microstrip line which is used to design matching networks and biasing circuits. The oscillation situation is resulted from the negative resistance which is generated from the cross-coupled structure, and the varactor of the VCO is realized by the capacitor in pHEMT device with reversed bias. The measured results show the oscillation center frequency of 30.07GHz with output power of -6.9 dBm and the phase noise of -95.81 dBc/Hz (@1 MHz offset). The tuning range of this VCO is 69 MHz (control voltage = 0.2 to 1.5 V) and the power consumption is 44mW. And the F.O.M of this VCO is -168.94 dBc/Hz. Besides, the relation between output power and load impedance of VCO at 30 GHz is observed by load-pull measurement system. The measured results show the maximum output power is about -3 dBm at ΓL = 0.5∠0 and the minimum output power is about -13 dBm at ΓL = 3 0.5∠2π (measurement range : 0 ≤ ≤ 0.5 L Γ and 0 ≤ ∠ ≤ 2π L Γ ). In the appendix, the novel CPW layout for cross-coupled structure is proposed for reducing the parasitic effect in high frequency circuit design.
    显示于类别:[電機工程研究所] 博碩士論文

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