現今通訊系統的應用中，對於高速操作與資訊流量的要求日益增加，此外因為SoC整合的需求，數位類比轉換器與數位信號處理電路的整合逐漸成為未來系統發展上一股重要的趨勢，因此電路實現上也勢必走向使用更先進的製程，針對於以上需求，本論文提出一項能應用於90奈米製程，低操作電壓、高速及高精準度的數位類比轉換器。 為了能達到高速運作的需求下，本文採取全差動電流式切換數位類比轉換器之架構，其中數位電路部份是以電流模式邏輯電路的架構來呈現，使得電路在邏輯切換時能得到較高的轉換速度，並能有效降低電路產生的偶次諧波失真與電源上的電壓抖動量。 在類比電路部份，因面臨低供應電壓及電晶體短通道效應之影響，使得在設計準確的電流源矩陣將變得非常因難，所以我們提出一個新的高準確主動式疊接電流鏡射架構，以提供電流源在切換的過程中，可同時確保電流之精確度，並能克服操作於1伏特時，輸出電壓振幅被壓縮及電流源輸出阻抗被嚴重限制之問題。 在晶片的實現上，本論文提出一個取樣頻率2GS/s之十位元數位類比轉換器，並實現在90nm CMOS 1P9M製程且操作電壓為1伏特。其中INL誤差範圍於±0.32LSB之內，而DNL誤差範圍於±0.13LSB，且輸入9.3MHz之數位碼時SFDR為65.1dB，而在982.2MHz時SFDR為54.4dB，整體的功率消耗為79mW，核心面積為 0.6mm × 0.416mm。上述規格已在晶片的模擬驗證上，證實此架構之可行性。 Nowadays the communication applications call for high speed operation. At the same time the SoC era continuously goes on, integrating digital-to-analog converter (DAC) with DSP becomes an important tendency. In view of this, this thesis proposes a digital-analog converter which can apply to 90um CMOS technology with low supply voltage、high speed and high solution applications. For high speed operation, the work employed a fully differential architecture. The logic operation of the digital circuits must match the DAC so as to achieve the faster conversion rate. Therefore current mode logic (CML) is often used in the high speed logic design. Besides, CML can effectively reduce the even harmonics distortion and power-ground bounce. In analog circuit part, output impedance is restricted by the low supply voltage and MOS short-channel effect. Designing an accurate current mirror for current source matrix, therefore, becomes extremely difficult. For 1 volt supply voltage considering the demands, a DAC with a new high precision active cascode mirror circuit is proposed in this work. The precision of this current source array can be obtained. In addition, the demand of low supply voltage and the influence of MOS short-channel effect can be overcome. The proposed 2GS/s 10bit DAC is implemented in 90nm CMOS 1P9M technology with the supply voltage of 1 volt. The INL is ±0.32LSB, and the DNL is ±0.13LSB. When the DAC operates at an input signal frequency of 9.3MHz, a SFDR of 65.1dB can be achieved. Moreover, a SFDR of 54.4dB can be gained when the DAC operates at 982.2MHz. The power consumption of the proposed design is 79mW. The core area is 0.6mm × 0.416mm
