Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： Double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22 nm node to enhance pattern printability. Previous work focused on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NCs) which cannot be resolved by any kind of stitch insertion. A design with NCs is not DPT-compliant and may fail the decomposition, resulting in design for manufacturability redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early-stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NCs in the layout as possible. The algorithm is based on iterative 1-D compaction and can easily be embedded into existing industrial compaction systems. The algorithm is then further applied to further reduce the number of stitches required for the decomposition process. Experimental results show that the proposed algorithm can significantly reduce the number of NCs by an average of 85% and reduce the number of stitches by an average of 39%, which may effectively increase the decomposition success rate for the next stage. 其他題名： TCAD 出版者： New York: IEEE 出版日期： 2012-05 出處： IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012-05, Vol.31 (5), p.703-716 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) May 2012 識別號： ISSN: 0278-0070 識別號： EISSN: 1937-4151 識別號： DOI: 10.1109/TCAD.2011.2179039 識別號： CODEN: ITCSDI
