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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/10402


    Title: 應用於隨機存取記憶體之有效良率及可靠度提升技術;Efficient Yield and Reliability Enhancement Techniques for Random Access Memories
    Authors: 盧星辰;Hsing-Chen Lu
    Contributors: 電機工程研究所
    Keywords: 隨機存取記憶體;線上透明測試/修復;診斷資料壓縮;Random Access Memories;Online Transparent Test/Repair;Diagnostic Data Compression
    Date: 2009-07-07
    Issue Date: 2009-09-22 12:15:33 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 良率和可靠度是設計奈米層級(nano-scale)晶片的兩個關鍵挑戰。嵌入式記憶體在現今的系統晶片(system-on-chip,SOC)中是重要的組件。因為嵌入式記憶體通常佔據很大比例的晶片面積,而且設計時會使用最小尺寸的電晶體和侵略性的設計規則(aggressive design rule),使得嵌入式記憶體的良率和可靠度將會主宰整個系統晶片,所以在系統晶片中,有效的提升嵌入式記憶體的良率和可靠度是非常重要的。 自我診斷(built-in self-diagnosis,BISD)和自我修復(built-in self-repair,BISR)電路是兩個主要提高嵌入式記憶體良率的技術。典型的自我診斷電路會將診斷資料序列輸出;在論文的第一部分,我們針對有錯誤更正碼(error correction code,ECC)的記憶體提出一個減少診斷資料的壓縮的方法,因為我們重複利用錯誤更正碼的電路來做壓縮,所提出的診斷資料壓縮方法能有效率的壓縮資料,而且付出的額外的面積成本非常低。 在論文的第二部分,我們針對有錯誤更正碼的記憶體提出一個透明自我修復(transparent BISR)的技術來提高記憶體的良率和可靠度,在量產階段,所提出的透明自我修復的技術可以執行離線測試/修復(off-line test/repair),在現場系統操作時,則可以執行線上測試卅修復(online test/repair)。執行線上測試卅修復時,我們使用透明測試(transparent test)來測試待測記憶體,並且使用離線測試/修復所剩下的備份元件(spare)來修復線上測試所測到的硬錯誤(hard fault),如此可以延長記憶體的可靠度。與其他現存的透明測試技術做比較,所提出的技術有以下優點:診斷錯誤位置的能力和低測試複雜度,另外,所提出的透明自我修復的技術面積成本不高,對於一個4K×39-bit的記憶體,大約只多出4.8%的面積。 在論文的第三部分,我們針對多個同質性記憶體(multiple homogeneous RAMs)提出一個分享式(shared)的透明自我測試和修復技術來減少面積成本,所提出的透明自我測試和修復技術建構一個分享式的錯誤更正碼記憶體來儲存待測記憶體的特徵值(signature),利用分時多工(time-multiplexing)的方法,我們可以一對一對記憶體做測試和修復,因為分享式的錯誤更正碼記憶體是被多個同質性記憶體所共享,所以面積成本相對降低。與傳統的透明自我測試方法比較,所提出的方法有診斷錯誤位置的能力,而且對於一個N×B-bit記憶體特徵預測時間(signature prediction phase)只要1N。  Yield and reliability are two key challenges for designing nano-scale chips. Embedded memory is one key component in modern system-on-chip (SoC) designs. It typically represents a significant portion of the chip area as well. Moreover, it is designed with the smallest transistors and aggressive design rules. Thus, the yield and reliability of embedded memories dominate that of SoCs. Therefore, efficient yield and reliability enhancement techniques for embedded memories are very important for SoCs. Built-in self-diagnosis (BISD) and built-in self-repair(BISR) are two key techniques for improving the yield of embedded memories. Typically, a BISD design exports diagnostic data serially. In the first part of this thesis, a diagnostic data compression technique is proposed to reduce the diagnostic data of a RAM with error correction code (ECC). By reusing the ECC circuit, the proposed approach can compress the diagnostic data efficiently with very low area cost. In the second part of this thesis, a transparent BISR scheme for RAMs with ECC is proposed to enhance the yield and reliability of RAMs. The transparent BISR scheme can perform off-line test/repair for RAMs in production phase. It also can perform online test/repair for RAMs in operation. In online test/repair mode, the transparent BISR scheme performs transparent march tests for the RAM under test and repairs the RAM cells with hard faults if some spares are unused after the off-line test/repair phase. This can prolong the reliability of the RAM. In comparison with existing transparent test approaches, the proposed transparent test approach has the following advantages: fault-location capability and low test complexity. Experimental results show that the area cost of the proposed transparent BISR scheme for RAMs with ECC is low—only about 4.8% for a 4K×39-bit SRAM. In the third part of this thesis, a shared transparent test and repair scheme for multiple homogeneous RAMs without ECC is proposed to reduce the area cost. In the shared transparent test and repair scheme, a shared code memory is designed to store the signature of a RAM under test. Thus, the RAMs sharing the code memory are tested and repaired one by one in a time-multiplexing method. Since the code memory is shared by multiple homogeneous RAMs, the area cost of the transparent test and repair scheme is reduced. In comparison with typical transparent BIST schemes, the proposed scheme has good fault location capability. The signature prediction phase is only 1N for an N×B-bit RAM.
    Appears in Collections:[電機工程研究所] 博碩士論文

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