具低相位雜訊之鎖相迴路設計; Design of Low Phase Noise Phase-locked-loop (PLL)

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Title:	具低相位雜訊之鎖相迴路設計;Design of Low Phase Noise Phase-locked-loop (PLL)
Authors:	柯幸姍;Hsing-shan Ko
Contributors:	電機工程研究所
Keywords:	鎖項迴路;相位雜訊;抖動;PLL;phase noise;jitter
Date:	2009-07-30
Issue Date:	2009-09-22 12:18:31 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	近年來晶片皆趨向單晶片系統(System-on-Chip)的方向，在整合系統中各個子電路區塊常出現操作時脈相位不同，而導致輸出資料錯誤，因此需要鎖相迴路(Phase-locked-Loop, PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減少輸出誤差。在時域的應用中，鎖相迴路最常被注意到的性能就是時脈抖動(Jitter)，而在頻域應用中，鎖相迴路最常被注意到的性能就是相位雜訊(Phase Noise)，兩者性能之間可做轉換，在時域上，當時脈抖動愈小時，其頻域上的相位雜訊也會愈好。在高速的系統中，電路對於雜訊十分敏感，故需有較高的雜訊免疫力才能保證系統的穩定度，有鑑於此，本論文提出具低相位雜訊之鎖相迴路設計，可產生3 GHz的頻率，在論文中將對鎖相迴路系統做詳細的雜訊分析，且解析影響整個系統的雜訊最主要的區塊，並對此區塊再做詳細電路的雜訊分析，藉由上述方式，本論文可提供出一低相位雜訊之鎖相迴路的設計方式。本晶片以TSMC 0.18 um 1P6M CMOS製程實現，輸出頻率為3 GHz，核心面積為0.034 mm2，所消耗的功率為23.7 mW，迴路鎖定時整體時脈輸出抖動量為3 ps(peak-to-peak)以內，RMS jittetr皆在600 fs以內，鎖定時間為600 ns，其環形電壓控制振盪器(Ring Voltage Control Oscillator, Ring-VCO) 在3GHz情況下的相位雜訊可高達-84.13dBc/Hz。 The chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system. The PLL is application to time domain it’s main performance is jitter. The PLL is application to frequency domain it’s main performance is phase noise. When phase noise is best means jitter is lower. In high-speed system, the circuit for very sensitive to noise. In this thesis, design of low phase noise is proposed. We analysis PLL noise source and find that main effects noise source block and noise analysis in block circuit. We use the TSMC 0.18 um 1P6M process with supplying 1.8V voltage in proposed PLL. The reference input frequency is 187.5MHz and the output frequency is 3GHz. The period jitter of output frequency is 3ps (pk-pk) RMS jitter is 600 fs. The power consumption of the proposed PLL is 23.7 mW at 3GHz and the Locking time of the PLL is 600ns. The core area is 0.034mm2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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