Performance-driven architectural synthesis for distributed register-file microarchitecture with inter-island delay

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Title:	Performance-driven architectural synthesis for distributed register-file microarchitecture with inter-island delay
Authors:	周景揚;HSU, Wan-Ling;LIN, Yen-Ting;JOU, Jing-Yang;HUANG, Juinn-Dar;CHEN, Chia-I
Contributors:	秘書室
Keywords:	Behavioral synthesis;distributed register-file;low-power;performance optimization;resource binding;scheduling
Date:	2012-01-01
Issue Date:	2026-04-23 11:58:05 (UTC+8)
Publisher:	Maruzen Co., Ltd/Maruzen Kabushikikaisha;The Institute of Electronics, Information and Communication Engineers
Abstract:	摘要： In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.(en) 其他題名： IEICE Trans. Fundamentals 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2012 出處： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2012/02/01, Vol.E95.A(2), pp.559-566 資源來源： J-STAGE Free 版權： 2012 The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 0916-8508 識別號： EISSN: 1745-1337 識別號： DOI: 10.1587/transfun.e95.a.559
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