Power-efficient instancy aware DRAM scheduling

NCUIR > administration > Office of Secretariat > journal & Dissertation > Item 987654321/104789

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/104789

Title:	Power-efficient instancy aware DRAM scheduling
Authors:	周景揚;JOU, Jing-Yang;LAI, Bo-Cheng Charles;PAN, Gung-Yu;LAI, Chih-Yen
Contributors:	秘書室
Keywords:	Clustering;Computer simulation;Controllers;DRAM;dynamic power management;Dynamic random access memory;energy-aware systems;Mathematical models;Performance degradation;Policies;Power management;scheduling
Date:	2015-04-01
Issue Date:	2026-04-23 11:58:08 (UTC+8)
Publisher:	Maruzen Co., Ltd/Maruzen Kabushikikaisha;The Institute of Electronics, Information and Communication Engineers
Abstract:	摘要： Nowadays, computer systems are limited by the power and memory wall. As the Dynamic Random Access Memory (DRAM) has dominated the power consumption in modern devices, developing power-saving approaches on DRAM has become more and more important. Among several techniques on different abstract levels, scheduling-based power management policies can be applied to existing memory controllers to reduce power consumption without causing severe performance degradation. Existing power-aware schedulers cluster memory requests into sets, so that the large portion of the DRAM can be switched into the power saving mode; however, only the target addresses are taken into consideration when clustering, while we observe the types (read or write) of requests can play an important role. In this paper, we propose two scheduling-based power management techniques on the DRAM controller: the inter-rank read-write aware clustering approach greatly reduces the active standby power, and the intra-rank read-write aware reordering approach mitigates the performance degradation. The simulation results show that the proposed techniques effectively reduce 75% DRAM power on average. Compared with the existing policy, the power reduction is 10% more on average with comparable or less performance degradation for the proposed techniques. 其他題名： IEICE Trans. Fundamentals 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2015 出處： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2015, Vol.E98.A(4), pp.942-953 資源來源： J-STAGE Free 版權： 2015 The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 1745-1337 識別號： ISSN: 0916-8508 識別號： EISSN: 1745-1337 識別號： DOI: 10.1587/transfun.E98.A.942
Appears in Collections:	[Office of Secretariat] journal & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	34	View/Open

社群 sharing

Loading...