中大學術數位典藏-NCU Institutional Repository-提供博碩士論文、考古題、期刊論文、研究計畫等下載:Item 987654321/106231
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 94201/94201 (100%)
Visitors : 81663677      Online Users : 3883
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version


    Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/106231


    Title: A 0.9-to 8-GHz VCO with a differential active inductor for multistandard wireline SerDes
    Authors: 龔存雄;Cheng, Kuo-Hsing;Hung, Cheng-Liang;Alex Gong, Cihun-Siyong;Liu, Jen-Chieh;Jiang, Bo-Qian;Sun, Shi-Yang
    Contributors: 資訊電機學院電機工程學系
    Keywords: Active inductors;Circuits;CMOS;Design engineering;Frequency measurement;Inductors;Phase locked loops;Phase noise;Power consumption;Q-factor;Redesign;SERD;Tuning;Voltage-controlled oscillators
    Date: 2014-08-01
    Issue Date: 2026-04-23 13:14:26 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
    Abstract: 摘要: This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive design, a quality (Q) factor enhancement technique has been also demonstrated to reduce the loss from the active inductor, leading to an appropriate phase noise over the entire tuning range. At a supply of 1.2 V, the fabricated LC-VCO provides a frequency tuning range of 0.9-8 GHz (160%) with power consumption of 3.2-19.1 mW. The measured phase noise is from -105 to -118 dBc/Hz at a 1-MHz offset. Realized in a fully integrated PLL chip, it occupies an active area of 0.08 × 0.16 mm 2 .
    其他題名: TCSII
    出版者: New York: IEEE
    出版日期: 2014-08
    出處: IEEE transactions on circuits and systems. II, Express briefs, 2014-08, Vol.61 (8), p.559-563
    資源來源: IEEE Electronic Library (IEL)
    版權: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2014
    識別號: ISSN: 1549-7747
    識別號: EISSN: 1558-3791
    識別號: DOI: 10.1109/TCSII.2014.2327451
    識別號: CODEN: ICSPE5
    Appears in Collections:[Department of Electrical Engineering] journal & Dissertation

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML27View/Open


    All items in NCUIR are protected by copyright, with all rights reserved.

    社群 sharing

    ::: Copyright National Central University. | 國立中央大學圖書館版權所有 | 收藏本站 | 設為首頁 | 最佳瀏覽畫面: 1024*768 | 建站日期:8-24-2009 :::
    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - 隱私權政策聲明