Institute of Electrical and Electronics Engineers Inc.;IEEE
摘要:
摘要： 3-D integration using through silicon via is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for the application of 3-D integration technology. However, yield will be a key challenge for the volume production of 3-D RAMs. In this paper, we present yield-enhancement techniques for 3-D RAMs. An interdie redundancy scheme is proposed to improve the yield of 3-D RAMs. Three stacking flows with respect to different bonding technologies for 3-D RAMs with interdie redundancy are proposed as well. Finally, a built-in self-repair (BISR) scheme is proposed to perform the repair of 3-D RAMs with interdie redundancies. The BISR circuits in two stacked dies can work together to allocate interdie redundancies. Simulation results show that the proposed yield-enhancement techniques can effectively improve the yield of 3-D RAMs. 其他題名： TCAD 出版者： IEEE 出版日期： 2013-04-01 出處： IEEE transactions on computer-aided design of integrated circuits and systems, 2013-04, Vol.32 (4), p.572-583 資源來源： IEEE Electronic Library (IEL) 識別號： ISSN: 0278-0070 識別號： EISSN: 1937-4151 識別號： DOI: 10.1109/TCAD.2012.2222882 識別號： CODEN: ITCSDI
