Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
摘要:
摘要： In this paper, we present design and analysis of an innovative low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked phase-locked loop (PLL) with self-aligned delay-locked loop in 65-nm CMOS technology. With the proposed innovative topology, the phase between the injection signal and the voltage-controlled oscillator in the PLL can be dynamically aligned to minimize the jitter over the variations. A modified theoretical model of the sub-harmonically injection-locked PLL with self-aligned injection is developed for the design methodology. The in-band phase noise of the sub-harmonically injection-locked PLL can be significantly improved using the self-aligned sub-harmonically injection-locked technique. The design considerations of the locking range, loop bandwidth, and frequency division ratio are addressed. At 10 GHz, the measured phase noise of the proposed PLL with self-aligned injection at 1-MHz offset is -130.2 dBc/Hz with a root-mean-square jitter of 44 fs. The total dc power consumption is 62.7 mW. From 10 ° C to 70 ° C, the measured phase noise at 1-MHz offset and jitter are better than -129 dBc/Hz and 48 fs, respectively. This work demonstrates excellent performance and good robustness over the variations, and it can be compared to the previously reported state-of-the-art sub-harmonically injection-locked PLLs. 其他題名： TMTT 出版者： New York, NY: IEEE 出版日期： 2014-03-01 出處： IEEE transactions on microwave theory and techniques, 2014-03, Vol.62 (3), p.543-555 資源來源： IEEE Xplore (NTUSG) 版權： 2015 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Mar 2014 識別號： ISSN: 0018-9480 識別號： EISSN: 1557-9670 識別號： DOI: 10.1109/TMTT.2014.2302747 識別號： CODEN: IETMAB
