Development pattern recognition model for the classification of circuit probe wafer maps on semiconductors

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/106613

Title:	Development pattern recognition model for the classification of circuit probe wafer maps on semiconductors
Authors:	洪炯宗;Chang, Cheng-Wei;Chao, Tsung-Ming;Horng, Jorng-Tzong;Lu, Chien-Feng;Yeh, Rong-Hwei
Contributors:	資訊電機學院資訊工程學系
Keywords:	Applied sciences;Classification;Clusters;Cover ratio;Data mining;defect patterns;Defects;Design. Technologies. Operation analysis. Testing;Electronics;Exact sciences and technology;Feature extraction;features extraction;Hough transform;Hough transformation;Image edge detection;integrated circuit (IC);Integrated circuit manufacture;Integrated circuits;Microelectronic fabrication (materials and surfaces technology);Pattern recognition;Semiconductor device modeling;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Semiconductors;zone ratio
Date:	2012-01-01
Issue Date:	2026-04-23 13:31:42 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;Piscataway, NJ: IEEE
Abstract:	摘要： Spatial defect patterns generated during integrated circuit (IC) manufacturing contain valuable information on the fabrication process and can help engineers identify the root causes of any defect. Classification of these defect patterns is crucial to improving reliability and yield during IC manufacturing. Accurate classification requires good feature selection in order to assist in identifying the defect cluster types. In this paper, we demonstrate that the linear Hough transformation, the circular Hough transformation incorporating the cover ratio approach, and the zone ratio approach, when used as feature-extraction techniques, are able to distinguish lines, various solid circle-like cluster patterns such as blobs and bull's-eyes, and various hollow circle-like cluster patterns such as rings and edges. On the basis of these features, in this paper we provide a comprehensive evaluation of several data-mining classification approaches in terms of performance and accuracy. The results obtained using both artificial and real manufacturing data demonstrate the potential of this approach for analyzing general defect patterns that are generated during the IC fabrication process. 其他題名： TCPMT 出版者： Piscataway, NJ: IEEE 出版日期： 2012-12-01 出處： IEEE transactions on components, packaging, and manufacturing technology (2011), 2012-12, Vol.2 (12), p.2089-2097 資源來源： IEEE Electronic Library (IEL) 版權： 2014 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2012 識別號： ISSN: 2156-3950 識別號： EISSN: 2156-3985 識別號： DOI: 10.1109/TCPMT.2012.2215327 識別號： CODEN: ITCPC8
Appears in Collections:	[Department of Computer Science and information Engineering] journal & Dissertation

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