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| 題名: | Analysis of single-trap-induced random telegraph noise on FinFET devices, 6T SRAM cell, and logic circuits |
| 作者: | 胡璧合;Fan, Ming-Long;Hu, Vita Pi-Ho;Chen, Yin-Nien;Su, Pin;Chuang, Ching-Te |
| 貢獻者: | 資訊電機學院電機工程學系 |
| 關鍵詞: | Applied sciences;Circuit properties;Digital circuits;Electric, optical and optoelectronic circuits;Electron traps;Electronic circuits;Electronic equipment and fabrication. Passive components, printed wiring boards, connectics;Electronics;Exact sciences and technology;FinFET;FinFETs;Integrated circuits;Integrated circuits by function (including memories and processors);Logic circuits;Logic gates;Random access memory;random telegraph noise (RTN);Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Silicon;static random access memory (SRAM);Transistors |
| 日期: | 2012-01-01 |
| 上傳時間: | 2026-04-23 13:31:45 (UTC+8) |
| 出版者: | Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE |
| 摘要: | 摘要： This paper analyzes the impacts of single-charged-trap-induced random telegraph noise (RTN) on FinFET devices in tied- and independent-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on trap location, EOT, and temperature is evaluated through 3-D atomistic TCAD simulation. It is observed that the charged trap located near the bottom of sidewall (gate) interface and in the middle region between the source and drain will result in the most significant impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We show that the planar BULK device, with larger subthreshold swing ( S.S. ) and comparable trap-induced V_{T} shift, exhibits less nominal RTN degradation than FinFET for traps placed in the worst position. However, the larger variability and surface conduction characteristic of the planar BULK device lead to broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the strong interaction between the charged trap and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the READ static noise margin of 64 possible combinations from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage (V_{\rm dd}) , the importance of RTN on subthreshold cell stability increases. Moreover, the leakage and delay of FinFET inverters, two-way nand, and two-to-one multiplexer are investigated using 3-D TCAD mixed-mode simulations. The RTN is found to cause \sim 24%-27% and \sim 13%-15% variations in leakage and delay at V_{ \rm dd} = \hbox{0.4}\ \hbox{V} , respectively, for the logic circuits evaluated.
其他題名： TED
出版者： New York, NY: IEEE
出版日期： 2012-08-01
出處： IEEE Transactions on Electron Devices, 2012-08, Vol.59 (8), p.2227-2234
資源來源： IEEE Electronic Library (IEL)
版權： 2015 INIST-CNRS
識別號： ISSN: 0018-9383
識別號： EISSN: 1557-9646
識別號： DOI: 10.1109/TED.2012.2200686
識別號： CODEN: IETDAI |
| 顯示於類別: | [電機工程學系] 期刊論文
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