Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory

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題名:	Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory
作者:	陳增益;Cheng, Sheng-Wei;Chang, Yuan-Hao;Chen, Tseng-Yi;Chang, Yu-Fen;Wei, Hsin-Wen;Shih, Wei-Kuan
貢獻者:	資訊電機學院資訊工程學系
關鍵詞:	Design analysis;Design engineering;Dynamics;Embedded systems;Leveling;Management;Memory management;Nonvolatile memory;operation efficiency;PCM main memory;Phase change materials;product warranty period;Random access memory;Very large scale integration;Warranties;Wear;wear leveling;Writing
日期:	2016-07-01
上傳時間:	2026-04-23 13:36:15 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:	摘要： Recently, phase change memory (PCM) has become a promising candidate to replace dynamic RAM as main memory due to its low power consumption, fast I/O performance, and byte addressability. Accompanied with the merits, the adoption of PCM may suffer from its physical characteristic of limited write endurance. Wear leveling is a well-known approach to address this issue. For PCM main memory, the design of wear leveling should stress operation efficiency and overhead reduction. Nevertheless, conventional designs are usually dedicated to prolonging the lifetime of PCM in the best effort. In this paper, we propose a novel perspective that, instead of valuing PCM lifetime exploitation as the first priority, we turn to satisfy the product warranty period. With such a paradigm shift, the management overhead of wear-leveling mechanisms could be reduced so as to achieve further enhancement of operation efficiency. To this end, we propose a warranty-aware page management design that introduces novel criteria used to determine the state of a page by taking both the product warranty period and the write cycles of a page into consideration. Theoretical analysis is also conducted to investigate the properties and performance of the proposed management. To show the effectiveness of the proposed design, we collected real traces by running SPEC2006 benchmarks with different write intensity workloads. The experimental results showed that our design reduced the overhead to one-third that of the state-of-the-art designs while still providing the same level of performance. 其他題名： TVLSI 出版者： New York: IEEE 出版日期： 2016-07 出處： IEEE transactions on very large scale integration (VLSI) systems, 2016-07, Vol.24 (7), p.2535-2547 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2015.2511147 識別號： CODEN: IEVSE9
顯示於類別:	[資訊工程學系] 期刊論文

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