Broadband complementary metal-oxide semiconductor single-pole-double-throw switch with improved power handling capability using dual-gate metal-oxide semiconductor field-effect transistors

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Title:	Broadband complementary metal-oxide semiconductor single-pole-double-throw switch with improved power handling capability using dual-gate metal-oxide semiconductor field-effect transistors
Authors:	辛裕明;Huang, Fan-Hsiu;Hsin, Yue-Ming
Contributors:	資訊電機學院電機工程學系
Keywords:	broadband complementary metal‐oxide semiconductor single‐pole‐double‐throw switch;CMOS integrated circuits;CMOS single‐pole‐double‐throw switch;dual‐gate metal‐oxide semiconductor field‐effect transistors;dual‐gate MOSFET;dual‐gate NMOS transistors;frequency 16 GHz to 67 GHz;Handling;large‐signal cascode model;Mathematical models;Metal oxide semiconductors;Metal oxides;millimetre‐wave applications;MOSFET;N-type semiconductors;Noise levels;parasitic gate‐to‐gate capacitance;power handling capability;radiocommunication;Semiconductors;substrate effect;Switches;travelling‐wave design;voltage distribution;voltage swing distribution
Date:	2015-01-01
Issue Date:	2026-04-23 13:36:52 (UTC+8)
Publisher:	Institution of Engineering and Technology;The Institution of Engineering and Technology
Abstract:	摘要： A broadband complementary metal-oxide semiconductor (CMOS) single-pole-double-throw (SPDT) switch based on a travelling-wave design with using dual-gate N-type metal-oxide semiconductor (NMOS) transistors is implemented in a 0.18 μm CMOS process for millimetre-wave applications. To further investigate the power handling capability in a dual-gate metal-oxide semiconductor field-effect transistor (MOSFET), this study analyses the mechanism of voltage swing distribution by using the proposed large-signal cascode model. Considering the parasitic gate-to-gate capacitance and the substrate effect, the simulations in this study can accurately predict the small-signal and power handling performances of the SPDT switch. The switch exhibits a measured 1 dB bandwidth of ∼51 GHz, ranging from 16 to 67 GHz with an insertion loss of 3.6 dB at 30 GHz. The measured isolation is also better than 22 dB. The measured power handling capability can achieve a 1 dB compression point at an input power of 23.8 dBm at 30 GHz with a negative body bias, and the simulation result shows a 1 dB compression point nearly 24 dBm. Based on the proposed model, the large-signal performances under different body biases can be significantly predicted when including the parasitic gate-to-gate capacitance in a dual-gate MOSFET. 出版者： The Institution of Engineering and Technology 出版日期： 2015-04-24 出處： IET microwaves, antennas & propagation, 2015-04, Vol.9 (6), p.502-507 資源來源： Wiley Online Library Open Access 版權： The Institution of Engineering and Technology 版權： 2015 The Institution of Engineering and Technology 識別號： ISSN: 1751-8725 識別號： ISSN: 1751-8733 識別號： EISSN: 1751-8733 識別號： DOI: 10.1049/iet-map.2013.0463
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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