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    Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/106707


    Title: Built-in self-repair scheme for the TSVs in 3-D ICs
    Authors: 李進福;Huang, Yu-Jen;Li, Jin-Fu
    Contributors: 資訊電機學院電機工程學系
    Keywords: 3-D integrated circuit (IC);built-in self-repair (BISR);Built-in self-test;Circuit faults;fuse;Fuses;Maintenance engineering;Redundancy;Through-silicon vias;through-silicon-via (TSV)
    Date: 2012-09-28
    Issue Date: 2026-04-23 13:37:50 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers Inc.;IEEE
    Abstract: 摘要: 3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.
    其他題名: TCAD
    出版者: IEEE
    出版日期: 2012-10-01
    出處: IEEE transactions on computer-aided design of integrated circuits and systems, 2012-10, Vol.31 (10), p.1600-1613
    資源來源: IEEE Electronic Library (IEL)
    識別號: ISSN: 0278-0070
    識別號: EISSN: 1937-4151
    識別號: DOI: 10.1109/TCAD.2012.2198475
    識別號: CODEN: ITCSDI
    Appears in Collections:[Department of Electrical Engineering] journal & Dissertation

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