Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： Built-in self-repair (BISR) techniques are widely used for the repair of embedded memories. One of the key components of a BISR circuit is the built-in redundancy-analysis (BIRA) module, which allocates redundancies according to the designed redundancy analysis algorithm. Thus, the BIRA module affects the repair rate of the BISR circuit. Existing BIRA schemes for RAMs can provide the optimal repair rate (the ratio of the number of repaired RAMs to the number of defective RAMs), but they require either high area cost or multiple test runs. This paper proposes a BIRA scheme for RAMs, which can provide the optimal repair rate using very low area cost and single test run. Furthermore, the BIRA is designed as reconfigurable such that it can be shared by multiple RAMs. Experimental results show that the area cost for implementing the proposed BIRA scheme is much lower than that of existing BIRA schemes with optimal repair rate. A test chip is also implemented to demonstrate the proposed BIRA scheme. 其他題名： TCAD 出版者： New York: IEEE 出版日期： 2012-06-01 出處： IEEE transactions on computer-aided design of integrated circuits and systems, 2012-06, Vol.31 (6), p.930-940 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jun 2012 識別號： ISSN: 0278-0070 識別號： EISSN: 1937-4151 識別號： DOI: 10.1109/TCAD.2011.2181510 識別號： CODEN: ITCSDI
