Institute of Electrical and Electronics Engineers Inc.;United States: IEEE
摘要:
摘要： In this paper, we present design and analysis of a K-band (18 to 26.5 GHz) low-phase-noise phase-locked loop (PLL) with the subharmonically injection-locked (SIL) technique. The phase noise of the PLL with subharmonic injection is investigated, and a modified phase noise model of the PLL with SIL technique is proposed. The theoretical calculations agree with the experimental results. Moreover, the phase noise of the PLL can be improved with the subharmonic injection. To achieve K-band operation with low dc power consumption, a divide-by-3 injection-locked frequency divider (ILFD) is used as a frequency prescaler. The measured phase noise of the PLL without injection is -110 dBc/Hz at 1 MHz offset at the operation frequency of 23.08 GHz. With the subharmonic injection, the measured phase noises at 1 MHz offset are -127, -127, and -119 dBc/Hz for the subharmonic injection number NINJ = 2, 3, and 4, respectively. Moreover, the performance of the proposed PLL with and without SIL technique can be compared with the reported advanced CMOS PLLs. 其他題名： T-UFFC 其他題名： IEEE Trans Ultrason Ferroelectr Freq Control 出版者： United States: IEEE 出版日期： 2014-12 出處： IEEE transactions on ultrasonics, ferroelectrics, and frequency control, 2014-12, Vol.61 (12), p.1927-1937 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2014 識別號： ISSN: 0885-3010 識別號： ISSN: 1525-8955 識別號： EISSN: 1525-8955 識別號： DOI: 10.1109/TUFFC.2012.005040 識別號： PMID: 25474769 識別號： CODEN: ITUCER
