Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
摘要:
摘要： Design and analysis of two high-speed high dynamic-range track-and-hold amplifiers are presented in this paper using 65- and 90-nm CMOS processes. To achieve remarkable circuit performance in the advanced CMOS regime, the cascode topology with an inductive peaking technique and the distributed topology are employed in the track-and-hold amplifiers. The circuit topology is investigated to obtain the design methodology of the CMOS high-speed high dynamic-range track-and-hold amplifier. The theoretical calculation is presented to completely verify the design concept. Moreover, the proposed CMOS track-and-hold amplifiers demonstrate wide bandwidth and good linearity. With a dc power consumption of 197 mW, the 65-nm CMOS track-and-hold amplifier features an input bandwidth of up to 7 GHz, a spurious-free dynamic range (SFDR) of 44.6 dB, and a total harmonic distortion (THD) of -44.5 dB. With a dc power consumption of 216 mW, the 90-nm CMOS track-and-hold amplifier features an input bandwidth of 19 GHz, an SFDR of 47.5 dB, and a THD of -44.5 dB. The proposed CMOS track-and-hold amplifiers are suitable for the high-resolution high-speed analog-to-digital converter with low dc supply voltage and power. 其他題名： TMTT 出版者： New York: IEEE 出版日期： 2015-09-01 出處： IEEE transactions on microwave theory and techniques, 2015-09, Vol.63 (9), p.2841-2853 資源來源： IEEE Electronic Library (IEL) (F) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2015 識別號： ISSN: 0018-9480 識別號： EISSN: 1557-9670 識別號： DOI: 10.1109/TMTT.2015.2457434 識別號： CODEN: IETMAB
