Maruzen Co., Ltd/Maruzen Kabushikikaisha;The Institute of Electronics, Information and Communication Engineers
摘要:
摘要： A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2k) operation with additions. No multiplications are needed. The value of (1+2k)N can be computed by adding N to its k-bit left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance. 其他題名： IEICE Trans. Fundamentals 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2015 出處： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2015, Vol.E98.A(4), pp.966-974 資源來源： J-STAGE Free 版權： 2015 The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 1745-1337 識別號： ISSN: 0916-8508 識別號： EISSN: 1745-1337 識別號： DOI: 10.1587/transfun.E98.A.966
