IEEE Circuits and Systems Society;Piscataway: IEEE
摘要:
摘要： In this work, we propose a mixed TFET-MOSFET 8T SRAM cell comprising MOSFET cross-coupled inverters, dedicated TFET read stack and TFET write access transistors for ultra-low voltage operation. Exploiting both the merits of TFET and MOSFET devices, the proposed SRAM cell provides significant improvement in SRAM stability, Vmin and performance. The stability and performance of the proposed cell are evaluated and compared with the conventional MOSFET 8T cell and pure TFET 8T cell using mixed-mode TCAD simulations based on published design rules for 22 nm technology node. Besides, the impacts of the device design of the proposed SRAM cell on the stability are also investigated. Various write-assist techniques to enhance the write-ability across VDD= 0.2 to 0.7 V for these SRAM cells are comparatively assessed. The results indicate that the proposed mixed TFET-MOSFET cell topology is viable for ultra-low voltage operation while MOSFET cell provides better stability and performance for high voltage operation. 其他題名： JETCAS 出版者： Piscataway: IEEE 出版日期： 2014-12-01 出處： IEEE journal on emerging and selected topics in circuits and systems, 2014-12, Vol.4 (4), p.389-399 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2014 識別號： ISSN: 2156-3357 識別號： EISSN: 2156-3365 識別號： DOI: 10.1109/JETCAS.2014.2361072 識別號： CODEN: IJESLY
