Evaluation of sub-0.2 V high-speed low-power circuits using hetero-channel MOSFET and tunneling FET devices

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/107197

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/107197

Title:	Evaluation of sub-0.2 V high-speed low-power circuits using hetero-channel MOSFET and tunneling FET devices
Authors:	胡璧合;Chen, Yin-Nien;Fan, Ming-Long;Hu, Vita Pi-Ho;Su, Pin;Chuang, Ching-Te
Contributors:	資訊電機學院電機工程學系
Keywords:	Capacitance;Circuits;Delay;Delays;Design engineering;Devices;Dynamics;Hetero-channel MOSFET;High speed;Inverters;Leakage currents;Logic gates;low-power;MOSFET;MOSFETs;tunnel FET;Tunneling
Date:	2014-01-01
Issue Date:	2026-04-23 13:59:40 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
Abstract:	摘要： This paper investigates the feasibility of sub-0.2 V high-speed low-power circuits with hetero-channel MOSFET and emerging Tunneling FET (TFET) devices. First, the device designs and characteristics of hetero-channel MOSFET and TFET devices are discussed and compared. Due to the significant leakage current of ultra-low VT hetero-channel MOSFET devices, assist-circuits are required for hetero-channel MOSFET-based circuits to operate at 0.2 V. Second, the delay, dynamic energy and the Standby power of hetero-channel TFET-based and MOSFET-based logic circuits including Inverter, NAND, BUS Driver, and Latch are analyzed and evaluated. The results indicate that hetero-channel TFET-based circuits with Dual Oxide (DOX) device design to reduce the Miller capacitance provide the potential to achieve high-speed low-power operation at VDD=0.2 V, while the use of assist-circuits in MOSFET-based design improves the delay and dynamic energy at the expense of increased device count, circuit area, and large Standby and sleep-mode leakage power. Finally, the impacts of temperature and process variations on TFET-based and MOSFET-based logic circuits are discussed. 其他題名： TCSI 出版者： New York: IEEE 出版日期： 2014-12-01 出處： IEEE transactions on circuits and systems. I, Regular papers, 2014-12, Vol.61 (12), p.3339-3347 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Dec 2014 識別號： ISSN: 1549-8328 識別號： EISSN: 1558-0806 識別號： DOI: 10.1109/TCSI.2014.2335032 識別號： CODEN: ITCSCH
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	14	View/Open

社群 sharing

Loading...