Hierarchical test integration methodology for 3-D ICs

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/107367

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/107367

Title:	Hierarchical test integration methodology for 3-D ICs
Authors:	李進福;Chou, Che-Wei;Li, Jin-Fu;Yu, Yun-Chao;Lo, Chih-Yen;Kwai, Ding-Ming;Chou, Yung-Fa
Contributors:	資訊電機學院電機工程學系
Keywords:	3D IC;BIST;Built-in self-test;Discrete Fourier transforms;Electronic equipment tests;hierarchical test;Integrated circuits;Registers;Switches;test interface;Test procedures;Three dimensional;Three-dimensional displays;through-silicon-via (TSV)
Date:	2015-07-01
Issue Date:	2026-04-23 14:10:13 (UTC+8)
Publisher:	IEEE Computer Society;Piscataway: IEEE Computer Society
Abstract:	摘要： In this paper, we propose a hierarchical test integration method for 3-D ICs. The method can handle a die with logic cores and memory cores. In addition to handle the test controlling of a hierarchical 3-D IC, furthermore, it also can support the test controlling of a 3-D IC with multiple towers. For a 3-D IC, the hierarchical test integration method uses two types of 1149.1-based test interfaces for the bottom die and nonbottom dies. Therefore, the test access ports for the two test interfaces are the same. Also, the number of required test pads of the proposed test interface is only 4. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. 其他題名： DTM 出版者： Piscataway: IEEE Computer Society 出版日期： 2015-08-01 出處： IEEE design and test, 2015-08, Vol.32 (4), p.59-70 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2015 識別號： ISSN: 2168-2356 識別號： EISSN: 2168-2364 識別號： DOI: 10.1109/MDAT.2015.2427257 識別號： CODEN: IDTCEC
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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