Impacts of work function variation and line-edge roughness on TFET and FinFET devices and 32-bit CLA circuits

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題名:	Impacts of work function variation and line-edge roughness on TFET and FinFET devices and 32-bit CLA circuits
作者:	胡璧合;Chen, Yin-Nien;Chen, Chien-Ju;Fan, Ming-Long;Hu, Vita;Su, Pin;Chuang, Ching-Te
貢獻者:	資訊電機學院電機工程學系
關鍵詞:	carry-lookahead adder (CLA);Circuits;Computer simulation;Delay;Devices;FinFET;line-edge-roughness (LER);Roughness;Tables (data);tunnel FET (TFET);Voltage;work function variation (WFV);Work functions
日期:	2015-05-21
上傳時間:	2026-04-23 14:14:05 (UTC+8)
出版者:	MDPI Multidisciplinary Digital Publishing Institute;Basel: MDPI AG
摘要:	摘要： In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices. 出版者： Basel: MDPI AG 出版日期： 2015-05-21 出處： Journal of low power electronics and applications, 2015-05, Vol.5 (2), p.101-115 資源來源： ProQuest Open Access Content Collection 版權： Copyright MDPI AG 2015 識別號： ISSN: 2079-9268 識別號： EISSN: 2079-9268 識別號： DOI: 10.3390/jlpea5020101
顯示於類別:	[電機工程學系] 期刊論文

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