Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs

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Title:	Independently-controlled-gate FinFET schmitt trigger sub-threshold SRAMs
Authors:	胡璧合;Hsieh, Chien-Yu;Fan, Ming-Long;Hu, V. P.;Su, Pin;Chuang, Ching-Te
Contributors:	資訊電機學院電機工程學系
Keywords:	Applied sciences;Computer simulation;Density;Design. Technologies. Operation analysis. Testing;Devices;Electronics;Exact sciences and technology;FinFET;FinFETs;Integrated circuits;Integrated circuits by function (including memories and processors);Layout;Logic gates;low power SRAM;Monte Carlo methods;Noise;Random access memory;Schmitt Trigger;Schmitt triggers;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Semiconductors;static noise margin;Static random access memory;sub-threshold SRAM;Switches;Three dimensional;Transistors;Wireless sensor networks
Date:	2012-01-01
Issue Date:	2026-04-23 14:16:48 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
Abstract:	摘要： In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations ( L eff , EOT, W fin , and H fin ) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio. 其他題名： TVLSI 出版者： New York, NY: IEEE 出版日期： 2012-07-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2012-07, Vol.20 (7), p.1201-1210 資源來源： IEEE Electronic Library (IEL) 版權： 2015 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jul 2012 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2011.2156435 識別號： CODEN: IEVSE9
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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