Interlaced switch boxes placement for three-dimensional FPGA architecture design

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/107600

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/107600

Title:	Interlaced switch boxes placement for three-dimensional FPGA architecture design
Authors:	許鈞瓏;Hsu, Chun-Lung;Huang, Yu-Sheng;Lee, Fong-Chao
Contributors:	資訊電機學院電機工程學系
Keywords:	area-delay product;delay-power product;field programmable gate array;interlaced
Date:	2012-05-01
Issue Date:	2026-04-23 14:18:37 (UTC+8)
Publisher:	John Wiley and Sons Ltd;Chichester, UK: John Wiley & Sons, Ltd
Abstract:	摘要： SUMMARY Three‐dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire‐length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two‐dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18‐µm CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM‐based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay‐power product improvement and 43% area‐delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd. A 3D FPGA architecture design with interlaced S2D‐boxes and S3Dboxes placement for performance efficiency is introduced (see Fig.). The proposed architecture based on interlaced switch boxes placement approach can approximately achieve 20% delay‐power product improvement and 43% area‐delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd. 其他題名： Int. J. Circ. Theor. Appl 出版者： Chichester, UK: John Wiley & Sons, Ltd 出版日期： 2012-05 出處： International journal of circuit theory and applications, 2012-05, Vol.40 (5), p.489-502 資源來源： Wiley Online Library 版權： Copyright © 2010 John Wiley & Sons, Ltd. 識別號： ISSN: 0098-9886 識別號： EISSN: 1097-007X 識別號： DOI: 10.1002/cta.739
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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