摘要： Constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units and they are prevalent in modern VLSI designs. This study presents efficient algorithms and their fast hardware implementation for performing multiplying-by-(2 super(k) plus or minus 1), or (2 super(k) plus or minus 1)N, operation with additions. No multiplications are needed. The value of (2 super(k) plus or minus 1)N can be computed by adding ( plus or minus N) to its k-bits left-shifted value 2 super(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper presents the unit cells for additions (UCAs). Results show that the UCA-based RCA achieves 34 % faster than the FA-based RCA. Further, in order to improve the speed performance with lower hardware cost, this paper also presents a simple and modular hybrid adder with the proposed UCA concept, where the hybrid adder takes the lower-bit carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the proposed hybrid adder achieved speed performance improvement while maintaining its modular and regular structure. 出版日期： 2016-01-01 出處： Journal of signal processing systems, 2016-01, Vol.82 (1), p.41-53 資源來源： SpringerLink - Journals 識別號： ISSN: 1939-8018 識別號： EISSN: 1939-8115 識別號： DOI: 10.1007/s11265-015-0978-4
