Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/107914

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Title:	Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
Authors:	陳竹一;Huang, Chien-Chih;Wey, Chin-Long;Chen, Jwu-E;Luo, Pei-Wen
Contributors:	資訊電機學院電機工程學系
Keywords:	Capacitors;Circuits;Criteria;Design engineering;Electronic systems;Optimization;Placement;Tolerances
Date:	2013-12-01
Issue Date:	2026-04-23 14:28:46 (UTC+8)
Publisher:	Association for Computing Machinery (ACM)
Abstract:	摘要： Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size. 出版日期： 2013-12 出處： ACM transactions on design automation of electronic systems, 2013-12, Vol.19 (1), p.1-13 資源來源： ACM Digital Library 識別號： ISSN: 1084-4309 識別號： EISSN: 1557-7309 識別號： DOI: 10.1145/2534394
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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