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    Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/107945


    Title: Performance-driven unit-capacitor placement of successive-approximation-register ADCs
    Authors: 陳竹一;Huang, Chien-Chih;Wey, Chin-Long;Chen, Jwu-E;Luo, Pei-Wen
    Contributors: 資訊電機學院電機工程學系
    Date: 2015-11-01
    Issue Date: 2026-04-23 14:29:18 (UTC+8)
    Publisher: Association for Computing Machinery (ACM)
    Abstract: 摘要: The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.
    出版日期: 2015-11-01
    出處: ACM transactions on design automation of electronic systems, 2015-11, Vol.21 (1), p.1-17
    資源來源: ACM Digital Library Complete
    識別號: ISSN: 1084-4309
    識別號: EISSN: 1557-7309
    識別號: DOI: 10.1145/2770872
    Appears in Collections:[Department of Electrical Engineering] journal & Dissertation

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