Photoelectrochemical liftoff of patterned sapphire substrate for fabricating vertical light-emitting diode

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/107963

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Title:	Photoelectrochemical liftoff of patterned sapphire substrate for fabricating vertical light-emitting diode
Authors:	姚毓峰;Hsieh, Chieh;Chen, Horng-Shyang;Liao, Che-Hao;Chen, Chih-Yen;Lin, Chun-Han;Lin, Cheng-Hung;Ting, Shao-Ying;Yao, Yu-Feng;Chen, Hao-Tsung;Kiang, Yean-Woei;Yang, Chih-Chung
Contributors:	資訊電機學院電機工程學系
Keywords:	Epitaxial growth;Epitaxial layers;Etching;Gallium nitride;Light emitting diodes;Patterned sapphire substrate;photoelectrochemical etching;Substrates;vertical light-emitting diode
Date:	2012-09-28
Issue Date:	2026-04-23 14:29:40 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;IEEE
Abstract:	摘要： A low-cost large-area effective sapphire substrate liftoff method based on the photoelectrochemical (PEC) etching technique is demonstrated. By preparing patterned sapphire substrate (PSS) with 1-D periodic grooves and an epitaxial structure with the grooves preserved to form tunnels, PEC electrolyte can flow along the tunnels to etch the bottom of the GaN layer for separating the PSS from the wafer-bonded epitaxial layer. Assisted by the device isolation procedure, the PSS liftoff of a quarter-wafer sample can be completed in 8 min. After a smoothing process of the exposed N-face surface after liftoff, a vertical light-emitting diode (LED) is fabricated for comparing its characteristics with those of a conventional LED. 其他題名： LPT 出版者： IEEE 出版日期： 2012-10-01 出處： IEEE Photonics Technology Letters, 2012-10, Vol.24 (19), p.1775-1777 資源來源： IEEE Xplore Digital Library 識別號： ISSN: 1041-1135 識別號： EISSN: 1941-0174 識別號： DOI: 10.1109/LPT.2012.2214476 識別號： CODEN: IPTLEL
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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