Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/108051

Title:	Proportional static-phase-error reduction for frequency-multiplier-based delay-locked-loop architecture
Authors:	鄭國興;CHENG, Kuo-Hsing;LIU, Jen-Chieh;TU, Yo-Hao
Contributors:	資訊電機學院電機工程學系
Keywords:	Architecture;Clocks;delay-locked-loop;Dynamic link libraries;edge-combiner;Electronics;frequency multiplier;Jitter;Phase error;Reduction;static-phase-error;time amplifier;Tuning
Date:	2016-06-01
Issue Date:	2026-04-23 14:33:26 (UTC+8)
Publisher:	Maruzen Co., Ltd/Maruzen Kabushikikaisha;The Institute of Electronics, Information and Communication Engineers
Abstract:	摘要： This paper proposes the proportional static-phase-error reduction (SPER) for the frequency-multiplier-based delay-locked-loop (DLL) architecture. The frequency multiplier (FM) can synthesize a combined clock to solve the high operational frequency of DLL. However, FM is sensitive to the static phase error of DLL. A SPER loop adopts a timing amplifier and a coarse-fine tuning technique to enhance the deterministic jitter of FM. The SPER loop proportionally reduces the static phase error and can extend the operating range of FM. 其他題名： IEICE Trans. Electron. 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2016-06-01 出處： IEICE Transactions on Electronics, 2016/06/01, Vol.E99.C(6), pp.655-658 資源來源： J-STAGE Free 版權： 2016 The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 1745-1353 識別號： ISSN: 0916-8524 識別號： EISSN: 1745-1353 識別號： DOI: 10.1587/transele.E99.C.655
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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