The Institute of Electronics, Information and Communication Engineers (IEICE);The Institute of Electronics, Information and Communication Engineers
摘要:
摘要： C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its soft-error tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element. 其他題名： IEICE Electron. Express 出版者： The Institute of Electronics, Information and Communication Engineers 出版日期： 2015 出處： IEICE Electronics Express, 2015, Vol.12(10), pp.20150268-20150268 版權： 2015 by The Institute of Electronics, Information and Communication Engineers 識別號： ISSN: 1349-2543 識別號： ISSN: 1349-9467 識別號： EISSN: 1349-2543 識別號： EISSN: 1349-9467 識別號： DOI: 10.1587/elex.12.20150268
