Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits

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Title:	Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
Authors:	胡璧合;Fan, Ming-Long;Yang, Shao-Yu;Hu, Vita Pi-Ho;Chen, Yin-Nien;Su, Pin;Chuang, Ching-Te
Contributors:	資訊電機學院電機工程學系
Keywords:	Applied sciences;Bias;Circuit properties;Design. Technologies. Operation analysis. Testing;Digital circuits;Electric, optical and optoelectronic circuits;Electronic circuits;Electronics;Exact sciences and technology;Germanium;Integrated circuits;Integrated circuits by function (including memories and processors);Logic circuits;Nanostructure;Nanowires;Noise;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Silicon;Static random access memory;Transistors;Tunnels (transportation)
Date:	2014-01-01
Issue Date:	2026-04-23 14:41:06 (UTC+8)
Publisher:	Elsevier Ltd.;Kidlington: Elsevier Ltd
Abstract:	摘要： •We review the impacts of random telegraph noise on FinFET, Ge/Si Nanowire FET, Tunnel FET (TFET) and related circuits.•For FinFET, trap in the middle between source/drain and bottom of sidewall interface shows larger impact.•The RTN in Ge Nanowire FET exhibits stronger drain bias dependence and may yield current increase.•TFET exhibits drastically higher sensitivity to RTN and significant IOFF degradation.•The possible RTN combinations due to trapping/detrapping in each device are discussed for SRAM and logic circuits. In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits. 出版者： Kidlington: Elsevier Ltd 出版日期： 2014-04-01 出處： Microelectronics and reliability, 2014-04, Vol.54 (4), p.698-711 資源來源： Elsevier ScienceDirect Journals Complete 版權： 2014 Elsevier Ltd 版權： 2015 INIST-CNRS 識別號： ISSN: 0026-2714 識別號： EISSN: 1872-941X 識別號： DOI: 10.1016/j.microrel.2013.12.026 識別號： CODEN: MCRLAS
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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