Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications

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Title:	Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications
Authors:	謝易叡;Yang, C. L.;Tsai, C. H.;Li, C. I.;Tzeng, C. Y.;Lin, G. P.;Chen, W. J.;Chin, Y. L.;Liao, C. I.;Chan, M.;Wu, J. Y.;Hsieh, E. R.;Guo, B. N.;Lu, S.;Colombeau, B.;Chung, S. S.;Chen, I. C.
Contributors:	資訊電機學院電機工程學系
Keywords:	Annealing;Applied sciences;Boron;Cryogenic implant;Cryogenics;Design. Technologies. Operation analysis. Testing;Electronics;Exact sciences and technology;Grain size;Implants;Integrated circuits;ion implantation;logic device;Microelectronic fabrication (materials and surfaces technology);MOSFET circuits;novel process technology;random dopant fluctuation;Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices;Threshold voltage;Transistors
Date:	2012-01-01
Issue Date:	2026-04-23 14:43:24 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
Abstract:	摘要： In this letter, we have demonstrated that cryogenic implant in the source and drain formation offers advantages for reducing the threshold voltage mismatch in pMOSFET. A discrete dopant profiling method is used to verify the presence of boron out-diffusion from the drain, which further induces the random dopant fluctuation. Results show that this boron out-diffusion can be greatly reduced in this new process. Two major factors in improving the device variability by cryogenic implant are discussed, i.e., the polysilicon grain size control and the embedded-SiGe dislocation defect reduction during source and drain formation. 其他題名： LED 出版者： New York, NY: IEEE 出版日期： 2012-10-01 出處： IEEE electron device letters, 2012-10, Vol.33 (10), p.1444-1446 資源來源： IEEE Electronic Library (IEL) 版權： 2015 INIST-CNRS 識別號： ISSN: 0741-3106 識別號： EISSN: 1558-0563 識別號： DOI: 10.1109/LED.2012.2209395 識別號： CODEN: EDLEDZ
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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