Testing Disturbance Faults in Various NAND Flash Memories

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > journal & Dissertation > Item 987654321/108377

Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/108377

Title:	Testing Disturbance Faults in Various NAND Flash Memories
Authors:	李進福;Hou, Chih-Sheng;Li, Jin-Fu
Contributors:	資訊電機學院電機工程學系
Keywords:	Algorithms;CAE) and Design;Circuits and Systems;Computer memory;Computer-Aided Engineering (CAD;Electrical Engineering;Engineering;Fault diagnosis;Product testing
Date:	2014-01-01
Issue Date:	2026-04-23 14:46:14 (UTC+8)
Publisher:	Springer Netherlands;Boston: Springer US
Abstract:	摘要： NAND flash memory is one popular non-volatile memory. Flash memory is prone to disturbance faults due to its specific mechanism of functional operations. Furthermore, different NAND flash memories might be different on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are proposed. 其他題名： J Electron Test 出版者： Boston: Springer US 出版日期： 2014-12-01 出處： Journal of electronic testing, 2014-12, Vol.30 (6), p.643-652 版權： Springer Science+Business Media New York 2014 識別號： ISSN: 0923-8174 識別號： EISSN: 1573-0727 識別號： DOI: 10.1007/s10836-014-5487-z
Appears in Collections:	[Department of Electrical Engineering] journal & Dissertation

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