American Institute of Physics;Melville: AIP Publishing
摘要:
摘要： A measurement methodology involving the synchronous switching of gate to source voltage and drain to source voltage (VDS) was proposed for determining the shift of threshold voltage after an AlGaN/GaN heterostructure transistor endures high VDS off-state stress. The measurement results indicated slow electron detrapping behavior. The trap level was determined as (EC – 0.6 eV). Simulation tool was used to analyze the measurement results. The simulation results were consistent with the experimental results; and a relationship between the buffer trap and threshold voltage shift over time was observed. 出版者： Melville: AIP Publishing 出版日期： 2014-01-20 出處： Applied Physics Letters, 2014-01, Vol.104 (3) 資源來源： AIP Journals (American Institute of Physics) 版權： 2014 AIP Publishing LLC. 識別號： ISSN: 0003-6951 識別號： EISSN: 1077-3118 識別號： DOI: 10.1063/1.4862669
