Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
摘要:
摘要： Optimized threshold voltage (Vt) design to enhance the variation immunity of high-performance (super-threshold) and low-voltage (near-/sub-threshold) 6 T SRAM cells is presented. For low-voltage SRAM cells operating at low Vdd, low-Vt design shows smaller variability, while the design tradeoff between performance and leakage should be considered. For high-performance SRAM cells operating at high Vdd, ultra-thin-body SOI SRAM cells with high-Vt design show smaller variability while sacrificing performance compared with the low-Vt design. Our study indicates that hetero-channel SRAM cells enable high-Vt design and exhibit improved Read/Write stability and performance, and maintain comparable RSNM variations for the high-performance SRAM applications. 其他題名： TED 出版者： New York, NY: IEEE 出版日期： 2013-01 出處： IEEE transactions on electron devices, 2013-01, Vol.60 (1), p.147-152 資源來源： IEEE Electronic Library (IEL) 版權： 2014 INIST-CNRS 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Jan 2013 識別號： ISSN: 0018-9383 識別號： EISSN: 1557-9646 識別號： DOI: 10.1109/TED.2012.2228863 識別號： CODEN: IETDAI
