Institute of Electrical and Electronics Engineers Inc.;New York, NY: IEEE
摘要:
摘要： This paper analyzes and compares the stability, margin, performance, and variability of ultrathin-body (UTB) SOI 6T SRAM cells operating near the subthreshold region with different threshold voltage (V th ) design. Our results indicate that UTB SOI 6T SRAM cell using low V th devices (|V th | = 0.19 V) shows a comparable read static noise margin (RSNM), 41% improvement in σRSNM, 84% improvement in write static noise margin (WSNM), and 67% improvement in σWSNM as compared with the case using higher V th devices (|V th | = 0.49 V). As V th decreases (work function moves to the band edge), the "cell" access time improves significantly with correspondingly higher standby leakage. For low V th devices (|V th | = 0.19 V), it is shown that lowering bit-line precharge voltage by 50 mV reduces the standby leakage by 20%. Our study suggests that the lower V th devices operating slightly into super-threshold region improve the stability/variability significantly and offer higher performance for ultralow voltage SRAM applications. 其他題名： TNANO 出版者： New York, NY: IEEE 出版日期： 2013-07-01 出處： IEEE transactions on nanotechnology, 2013-07, Vol.12 (4), p.524-531 資源來源： IEEE Electronic Library (IEL) 版權： 2015 INIST-CNRS 識別號： ISSN: 1536-125X 識別號： EISSN: 1941-0085 識別號： DOI: 10.1109/TNANO.2011.2105278 識別號： CODEN: ITNECU
