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    請使用永久網址來引用或連結此文件: https://ir.lib.ncu.edu.tw/handle/987654321/108483


    題名: Trap-profile extraction using high-voltage capacitance-voltage measurement in AlGaN/GaN heterostructure field-effect transistors with field plates
    作者: 綦振瀛;Liao, Wen-Chia;Chyi, Jen-Inn;Hsin, Yue-Ming
    貢獻者: 資訊電機學院電機工程學系
    關鍵詞: AlGaN/GaN heterostructure field-effect transistors (HFETs);Aluminum gallium nitride;Charge carrier processes;current collapse;Gallium nitride;HEMTs;Logic gates;MODFETs;Stress measurement;transient capacitance-voltage (C-V) measurement
    日期: 2015-01-01
    上傳時間: 2026-04-23 14:51:12 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers Inc.;IEEE
    摘要: 摘要: A measurement methodology involving high-voltage capacitance-voltage (C-V) was proposed to determine the trapping profile of a stressed AlGaN/GaN heterostructure field-effect transistor (HFET). Comparing the curves between initial (device without stress) and stressed (device with stress) C-V measurements revealed that the transient behavior was dominated by ionized acceptor-like traps, and the trapping profile within the high drain-to-source OFF-state stressed AlGaN/GaN HFET could be deduced.
    其他題名: TED
    出版者: IEEE
    出版日期: 2015-03-01
    出處: IEEE transactions on electron devices, 2015-03, Vol.62 (3), p.835-839
    資源來源: IEEE Electronic Library (IEL)
    識別號: ISSN: 0018-9383
    識別號: EISSN: 1557-9646
    識別號: DOI: 10.1109/TED.2015.2395720
    識別號: CODEN: IETDAI
    顯示於類別:[電機工程學系] 期刊論文

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