Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/108507

Title:	Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement
Authors:	鄭政誠;Lin, Bing-Yang;Chiang, Wan-Ting;Wu, Cheng-Wen;Lee, Mincent;Lin, Hung-Chih;Peng, Ching-Nen;Wang, Min-Jer
Contributors:	文學院歷史研究所
Keywords:	3D DRAM;Algorithm design and analysis;built-in self-repair (BISR);Built-in self-test;built-in self-test (BIST);Channels;Circuit faults;Configurable;Dies;Dynamic random access memory;Electronic equipment tests;Maintenance engineering;memory testing;Random access memory;Redundancy;redundancy analysis (RA);redundancy repair;Stacking;Three dimensional;Three-dimensional displays;yield improvement
Date:	2016-04-01
Issue Date:	2026-04-23 14:52:39 (UTC+8)
Publisher:	IEEE Computer Society;Piscataway: IEEE Computer Society
Abstract:	摘要： Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channel-based 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes. 其他題名： DTM 出版者： Piscataway: IEEE Computer Society 出版日期： 2016-04-01 出處： IEEE design and test, 2016-04, Vol.33 (2), p.30-39 資源來源： IEEE Electronic Library (IEL) 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2016 識別號： ISSN: 2168-2356 識別號： EISSN: 2168-2364 識別號： DOI: 10.1109/MDAT.2015.2455347 識別號： CODEN: IDTCEC
Appears in Collections:	[Graduate Institute of History ] journal & Dissertation

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