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    Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/108510


    Title: DArT: A component-based DRAM area, power, and timing modeling tool
    Authors: 鄭政誠;Shih, Hsiu-Chuan;Luo, Pei-Wen;Yeh, Jen-Chieh;Lin, Shu-Yen;Kwai, Ding-Ming;Lu, Shih-Lien;Schaefer, Andre;Wu, Cheng-Wen
    Contributors: 文學院歷史研究所
    Keywords: Accuracy;Architecture;Arrays;Delays;Design engineering;Deviation;Dynamic random access memory;Flexibility;Integrated circuit modeling;Random access memory;Time measurements;Wires
    Date: 2014-01-01
    Issue Date: 2026-04-23 14:52:42 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
    Abstract: 摘要: DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.
    其他題名: TCAD
    出版者: New York: IEEE
    出版日期: 2014-09-01
    出處: IEEE transactions on computer-aided design of integrated circuits and systems, 2014-09, Vol.33 (9), p.1356-1369
    資源來源: IEEE Electronic Library (IEL)
    版權: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Sep 2014
    識別號: ISSN: 0278-0070
    識別號: EISSN: 1937-4151
    識別號: DOI: 10.1109/TCAD.2014.2323203
    識別號: CODEN: ITCSDI
    Appears in Collections:[Graduate Institute of History ] journal & Dissertation

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