Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base

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Title:	Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base
Authors:	鄭政誠;Chi, Chun-Chuan;Marinissen, Erik Jan;Goel, Sandeep Kumar;Wu, Cheng-Wen
Contributors:	文學院歷史研究所
Keywords:	2.5-D IC;3-D IC;Algorithms;Architecture;Costs;design for test;Dies;Integrated circuit interconnections;Interconnections;interposer;Optimization;Optimization algorithms;Pins;post-bond test;Silicon;test access mechanism;Testing;Three dimensional;through-silicon via (TSV);Very large scale integration;Wire;Wires
Date:	2014-11-01
Issue Date:	2026-04-23 14:53:27 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers Inc.;New York: IEEE
Abstract:	摘要： Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower power consumption than traditional 2-D ICs. A practical TSV-based 3-D integration approach is to place multiple dies (or die stacks) side by side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects. In this paper, we propose a post-bond design-for-test architecture and a test strategy for such interposer-based 3-D ICs. Functional package pins and interconnects are reused to build multibit parallel test access mechanisms (PTAMs), which provide post-bond test access with no or low extra area costs. Four PTAM architectures are presented, and the corresponding PTAM optimization algorithms are proposed which can quickly identify the best PTAM configuration to achieve the shortest test time. We also propose an algorithm for adding dedicated test interconnects to improve test bandwidth at the expense of extra microbumps and metal wires. Experimental results show that the proposed techniques are effective in test length (and therefore test time) reduction. Moreover, cost-benefit analysis results suggest that our approaches have lower total test costs compared with a base-case one-bit JTAG-only solution. 其他題名： TVLSI 出版者： New York: IEEE 出版日期： 2014-11-01 出處： IEEE transactions on very large scale integration (VLSI) systems, 2014-11, Vol.22 (11), p.2388-2401 資源來源： IEEE Xplore Digital Library 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nov 2014 識別號： ISSN: 1063-8210 識別號： EISSN: 1557-9999 識別號： DOI: 10.1109/TVLSI.2013.2293192 識別號： CODEN: IEVSE9
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