On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs

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Please use this identifier to cite or link to this item: https://ir.lib.ncu.edu.tw/handle/987654321/108530

Title:	On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs
Authors:	鄭政誠;Chi, Chun-Chuan;Lin, Bing-Yang;Wu, Cheng-Wen;Wang, Min-Jer;Lin, Hung-Chih;Peng, Ching-Neng
Contributors:	文學院歷史研究所
Keywords:	3D-IC;Built-in self-test;Circuits;defect diagnosis;Diagnosis;Integrated circuit interconnections;Integrated circuits;interconnect BIST;interconnect repair;Interconnections;interposer test;Maintenance;Maintenance engineering;Redundancy;Repairing;Silicon;Three dimensional;Three dimensional displays;Through-silicon vias;TSV;yield enhancement
Date:	2014-01-01
Issue Date:	2026-04-23 14:53:35 (UTC+8)
Publisher:	IEEE Computer Society;Piscataway: IEEE Computer Society
Abstract:	摘要： This article discusses a design-for-test (DFT) architecture for detecting and repairing faulty interconnects in 3-D IC circuits utilizing through silicon via (TSV) and interposer technology. The yield of such circuits depends highly on the ability to have functioning interconnects which connect the various dies. The authors also propose a built-in-self-test (BIST) framework to enable at-speed testing of such interconnects. 其他題名： DTM 出版者： Piscataway: IEEE Computer Society 出版日期： 2014-08-01 出處： IEEE design and test, 2014-08, Vol.31 (4), p.16-26 資源來源： IEEE Xplore 版權： Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Aug 2014 識別號： ISSN: 2168-2356 識別號： EISSN: 2168-2364 識別號： DOI: 10.1109/MDAT.2014.2304437 識別號： CODEN: IDTCEC
Appears in Collections:	[Graduate Institute of History ] journal & Dissertation

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