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    請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/29483


    題名: SYNTHESIZING NESTED LOOP ALGORITHMS USING NONLINEAR TRANSFORMATION METHOD
    作者: SHEU,JP;CHANG,CY
    貢獻者: 電機工程研究所
    關鍵詞: PARALLEL PROCESSOR BOUNDS;FORTRAN-LIKE LOOPS;TIME
    日期: 1991
    上傳時間: 2010-06-29 20:25:54 (UTC+8)
    出版者: 中央大學
    摘要: In this paper, we synthesize nested For-loops with partitions on the innermost loop. First, we present a nonlinear transformation algorithm to exploit the parallelism of the For-loops. By the mapping of nonlinear transformation, iterations of For-loops can be executed in a parallel form. The proposed algorithm is useful in exploiting the parallelism of For-loops with one or more partitions on the innermost loop. Then, we also design algorithms to partition and map the nested For-loops onto the fixed size systolic arrays. Based on the time and space mapping schemes, all the iterations of For-loops can be correctly executed on the array processors in a parallel form.
    關聯: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
    顯示於類別:[電機工程研究所] 期刊論文

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